From: Pavel Machek <pavel@denx.de>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 05/11] clk: fixed: Remove Allwinner A10 special-case logic
Date: Wed, 22 Nov 2023 22:04:50 +0100 [thread overview]
Message-ID: <ZV5s8nrOSGpcravo@duo.ucw.cz> (raw)
In-Reply-To: <20231122142819.203737-6-biju.das.jz@bp.renesas.com>
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Hi!
> From: Samuel Holland <samuel@sholland.org>
>
> commit c33ed61249dc54e7cf2137c04462883560375b77 upstream.
>
> This compatible is part of the legacy sunxi clock support, and has not
> been used since commit 6b48644b1d29 ("ARM: gr8: Convert to CCU") in
> October 2016. Since supporting this compatible adds some overhead to
> generic clock code, let's clean it up.
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -203,16 +203,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
> EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
>
> #ifdef CONFIG_OF
> -static const struct of_device_id set_rate_parent_matches[] = {
> - { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
> - { /* Sentinel */ },
> -};
This is still mentioned in
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2023-11-22 21:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 14:28 [PATCH 5.10.y-cip 00/11] Add versa3 clk generator support Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 01/11] dt-bindings: clock: Add Renesas versa3 clock generator bindings Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 02/11] dt-bindings: clock: versaclock3: Add description for #clock-cells property Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 03/11] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 04/11] clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 05/11] clk: fixed: Remove Allwinner A10 special-case logic Biju Das
2023-11-22 21:04 ` Pavel Machek [this message]
2023-11-22 14:28 ` [PATCH 5.10.y-cip 06/11] clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw() Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 07/11] clk: Add support for versa3 clock driver Biju Das
2023-11-22 21:07 ` Pavel Machek
2023-11-23 8:30 ` Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 08/11] clk: vc3: Fix 64 by 64 division Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 09/11] clk: vc3: Fix output clock mapping Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 10/11] clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum Biju Das
2023-11-22 14:28 ` [PATCH 5.10.y-cip 11/11] arm64: dts: renesas: rz-smarc: Use versa3 clk for audio mclk Biju Das
2023-11-22 21:03 ` [PATCH 5.10.y-cip 00/11] Add versa3 clk generator support Pavel Machek
2023-11-23 7:25 ` Biju Das
2023-11-23 22:15 ` nobuhiro1.iwamatsu
2023-11-24 8:42 ` Pavel Machek
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