* [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements
@ 2024-02-02 11:37 Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Biju Das
` (7 more replies)
0 siblings, 8 replies; 10+ messages in thread
From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
This patch series aims to improve versa3 clock driver.
All the patches are cherry-picked from the mainline.
Biju Das (6):
arm64: defconfig: Enable Renesas VersaClock 3 clock generator config
clk: versaclock3: Update vc3_get_div() to avoid divide by zero
clk: versaclock3: Avoid unnecessary padding
clk: versaclock3: Use u8 return type for get_parent() callback
clk: versaclock3: Add missing space between ')' and '{'
clk: versaclock3: Drop ret variable
arch/arm64/configs/defconfig | 1 +
drivers/clk/clk-versaclock3.c | 88 ++++++++++++++++-------------------
2 files changed, 41 insertions(+), 48 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero Biju Das ` (6 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit ac2453d06c768b0604e231d6effabc1c405bd802 upstream. Enable the config for the Renesas VersaClock 3 programmable clock generator, as it is populated on RZ/{G2L,G2LC} and RZ/V2L SMARC EVKs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230824083006.88944-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0b746403e93a..b43f74c282d3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1055,6 +1055,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_VC3=y CONFIG_COMMON_CLK_VC5=y CONFIG_COMMON_CLK_BD718XX=m CONFIG_CLK_RASPBERRYPI=m -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6.1.y-cip 2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 3/6] clk: versaclock3: Avoid unnecessary padding Biju Das ` (5 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit eb16ddb838dd8602961b5fc17d1350cd41ae69e0 upstream. Update vc3_get_div() to avoid divide by zero operation on vc3_div_round_rate() by returning1, if there is no table match found. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 880702f6a171..2aa5f5f34ddd 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -477,7 +477,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table, if (clkt->val == val) return clkt->div; - return 0; + return 1; } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6.1.y-cip 3/6] clk: versaclock3: Avoid unnecessary padding 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 4/6] clk: versaclock3: Use u8 return type for get_parent() callback Biju Das ` (4 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit 1e8ce92afdbf2dafa345a9b1d91fb14a1487dc7f upstream. Move long/pointer variables at the beginning of struct to avoid unnecessary padding. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 2aa5f5f34ddd..ac5f2c43b595 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -148,16 +148,16 @@ struct vc3_pfd_data { }; struct vc3_pll_data { + unsigned long vco_min; + unsigned long vco_max; u8 num; u8 int_div_msb_offs; u8 int_div_lsb_offs; - unsigned long vco_min; - unsigned long vco_max; }; struct vc3_div_data { - u8 offs; const struct clk_div_table *table; + u8 offs; u8 shift; u8 width; u8 flags; -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6.1.y-cip 4/6] clk: versaclock3: Use u8 return type for get_parent() callback 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das ` (2 preceding siblings ...) 2024-02-02 11:37 ` [PATCH 6.1.y-cip 3/6] clk: versaclock3: Avoid unnecessary padding Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 5/6] clk: versaclock3: Add missing space between ')' and '{' Biju Das ` (3 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit a72956c82eebd138764fa214968571b0e455378e upstream. The return type of get_parent() member in struct clk_ops is u8. Use same return type for corresponding callback function as well. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index ac5f2c43b595..9d7c3d1249b7 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -210,7 +210,7 @@ static const struct clk_div_table div3_divs[] = { static struct clk_hw *clk_out[6]; -static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw) +static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; @@ -440,7 +440,7 @@ static const struct clk_ops vc3_pll_ops = { .set_rate = vc3_pll_set_rate, }; -static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw) +static u8 vc3_div_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; @@ -558,7 +558,7 @@ static int vc3_clk_mux_determine_rate(struct clk_hw *hw, return ret; } -static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw) +static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6.1.y-cip 5/6] clk: versaclock3: Add missing space between ')' and '{' 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das ` (3 preceding siblings ...) 2024-02-02 11:37 ` [PATCH 6.1.y-cip 4/6] clk: versaclock3: Use u8 return type for get_parent() callback Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:37 ` [PATCH 6.1.y-cip 6/6] clk: versaclock3: Drop ret variable Biju Das ` (2 subsequent siblings) 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit 123511056263bf1dce005f56bf76ba610d83e157 upstream. Add missing space between ')' and '{' for hw.init initialization. While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a->0xa. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-5-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 44 +++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 9d7c3d1249b7..a718c23d96b4 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -37,7 +37,7 @@ #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) #define VC3_PLL1_VCO_N_DIVIDER 0x9 -#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a +#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa #define VC3_OUT_DIV1_DIV2_CTRL 0xf @@ -611,7 +611,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_PLL_OP_CTRL, .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -624,7 +624,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -642,7 +642,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL1_M_DIV1, .mdiv2_bitmsk = VC3_PLL1_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd1", .ops = &vc3_pfd_ops, .parent_data = &(const struct clk_parent_data) { @@ -659,7 +659,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL2_M_DIV1, .mdiv2_bitmsk = VC3_PLL2_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -676,7 +676,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL3_M_DIV1, .mdiv2_bitmsk = VC3_PLL3_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -697,7 +697,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL1_VCO_MIN, .vco_max = VC3_PLL1_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll1", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -715,7 +715,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL2_VCO_MIN, .vco_max = VC3_PLL2_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll2", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -733,7 +733,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL3_VCO_MIN, .vco_max = VC3_PLL3_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll3", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -766,7 +766,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV1_MUX], @@ -779,7 +779,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_PLL3_CHARGE_PUMP_CTRL, .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV3_MUX], @@ -792,7 +792,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_OUTPUT_CTR, .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV4_MUX], @@ -811,7 +811,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -829,7 +829,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div2", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -847,7 +847,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -865,7 +865,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -883,7 +883,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div5", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -901,7 +901,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE1_DIV4_CTRL, .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -917,7 +917,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE2_CTRL_REG0, .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -933,7 +933,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE3_DIFF1_CTRL_REG, .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se3_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -949,7 +949,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF1_CTRL_REG, .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -965,7 +965,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF2_CTRL_REG, .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 6.1.y-cip 6/6] clk: versaclock3: Drop ret variable 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das ` (4 preceding siblings ...) 2024-02-02 11:37 ` [PATCH 6.1.y-cip 5/6] clk: versaclock3: Add missing space between ')' and '{' Biju Das @ 2024-02-02 11:37 ` Biju Das 2024-02-02 11:45 ` [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Pavel Machek 2024-02-02 12:08 ` nobuhiro1.iwamatsu 7 siblings, 0 replies; 10+ messages in thread From: Biju Das @ 2024-02-02 11:37 UTC (permalink / raw) To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar commit b08fa385937c1b6baae24683f6430230212b43e5 upstream. Drop ret variable from vc3_clk_mux_determine_rate(). While at it, return the value returned by regmap_* wherever possible instead of returning 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-6-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/clk-versaclock3.c | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index a718c23d96b4..f0222b63755d 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -226,9 +226,8 @@ static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; - regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, - index ? pfd_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, + index ? pfd_mux->bitmsk : 0); } static const struct clk_ops vc3_pfd_mux_ops = { @@ -456,10 +455,8 @@ static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; - regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, - index ? div_mux->bitmsk : 0); - - return 0; + return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, + index ? div_mux->bitmsk : 0); } static const struct clk_ops vc3_div_mux_ops = { @@ -524,10 +521,9 @@ static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, value = divider_get_val(rate, parent_rate, div_data->table, div_data->width, div_data->flags); - regmap_update_bits(vc3->regmap, div_data->offs, - VC3_DIV_MASK(div_data->width) << div_data->shift, - value << div_data->shift); - return 0; + return regmap_update_bits(vc3->regmap, div_data->offs, + VC3_DIV_MASK(div_data->width) << div_data->shift, + value << div_data->shift); } static const struct clk_ops vc3_div_ops = { @@ -539,11 +535,9 @@ static const struct clk_ops vc3_div_ops = { static int vc3_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - int ret; int frc; - ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); - if (ret) { + if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { /* The below check is equivalent to (best_parent_rate/rate) */ if (req->best_parent_rate >= req->rate) { frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, @@ -552,10 +546,9 @@ static int vc3_clk_mux_determine_rate(struct clk_hw *hw, return clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); } - ret = 0; } - return ret; + return 0; } static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) @@ -574,9 +567,8 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; - regmap_update_bits(vc3->regmap, clk_mux->offs, - clk_mux->bitmsk, index ? clk_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, + index ? clk_mux->bitmsk : 0); } static const struct clk_ops vc3_clk_mux_ops = { -- 2.25.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das ` (5 preceding siblings ...) 2024-02-02 11:37 ` [PATCH 6.1.y-cip 6/6] clk: versaclock3: Drop ret variable Biju Das @ 2024-02-02 11:45 ` Pavel Machek 2024-02-02 12:08 ` nobuhiro1.iwamatsu 7 siblings, 0 replies; 10+ messages in thread From: Pavel Machek @ 2024-02-02 11:45 UTC (permalink / raw) To: Biju Das; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Lad Prabhakar [-- Attachment #1: Type: text/plain, Size: 405 bytes --] Hi! > This patch series aims to improve versa3 clock driver. > > All the patches are cherry-picked from the mainline. Series looks okay to me, I can apply it if there are no other comments and if it passes testing. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements 2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das ` (6 preceding siblings ...) 2024-02-02 11:45 ` [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Pavel Machek @ 2024-02-02 12:08 ` nobuhiro1.iwamatsu 2024-02-05 11:23 ` Pavel Machek 7 siblings, 1 reply; 10+ messages in thread From: nobuhiro1.iwamatsu @ 2024-02-02 12:08 UTC (permalink / raw) To: biju.das.jz, cip-dev, pavel; +Cc: prabhakar.mahadev-lad.rj Hi all, > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Friday, February 2, 2024 8:38 PM > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□ > ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> > Subject: [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements > > This patch series aims to improve versa3 clock driver. > > All the patches are cherry-picked from the mainline. > > Biju Das (6): > arm64: defconfig: Enable Renesas VersaClock 3 clock generator config > clk: versaclock3: Update vc3_get_div() to avoid divide by zero > clk: versaclock3: Avoid unnecessary padding > clk: versaclock3: Use u8 return type for get_parent() callback > clk: versaclock3: Add missing space between ')' and '{' > clk: versaclock3: Drop ret variable > > arch/arm64/configs/defconfig | 1 + > drivers/clk/clk-versaclock3.c | 88 > ++++++++++++++++------------------- > 2 files changed, 41 insertions(+), 48 deletions(-) I reviewed this series, so LGTM. I will apply this series, if we have no other comments. Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements 2024-02-02 12:08 ` nobuhiro1.iwamatsu @ 2024-02-05 11:23 ` Pavel Machek 0 siblings, 0 replies; 10+ messages in thread From: Pavel Machek @ 2024-02-05 11:23 UTC (permalink / raw) To: nobuhiro1.iwamatsu; +Cc: biju.das.jz, cip-dev, pavel, prabhakar.mahadev-lad.rj [-- Attachment #1: Type: text/plain, Size: 1149 bytes --] Hi! > > This patch series aims to improve versa3 clock driver. > > > > All the patches are cherry-picked from the mainline. > > > > Biju Das (6): > > arm64: defconfig: Enable Renesas VersaClock 3 clock generator config > > clk: versaclock3: Update vc3_get_div() to avoid divide by zero > > clk: versaclock3: Avoid unnecessary padding > > clk: versaclock3: Use u8 return type for get_parent() callback > > clk: versaclock3: Add missing space between ')' and '{' > > clk: versaclock3: Drop ret variable > > > > arch/arm64/configs/defconfig | 1 + > > drivers/clk/clk-versaclock3.c | 88 > > ++++++++++++++++------------------- > > 2 files changed, 41 insertions(+), 48 deletions(-) > > I reviewed this series, so LGTM. > I will apply this series, if we have no other comments. > > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Thanks for review, it tests okay, so I applied the series and pushed it out. Best regards, Pavel -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
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2024-02-02 11:37 [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 1/6] arm64: defconfig: Enable Renesas VersaClock 3 clock generator config Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 2/6] clk: versaclock3: Update vc3_get_div() to avoid divide by zero Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 3/6] clk: versaclock3: Avoid unnecessary padding Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 4/6] clk: versaclock3: Use u8 return type for get_parent() callback Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 5/6] clk: versaclock3: Add missing space between ')' and '{' Biju Das
2024-02-02 11:37 ` [PATCH 6.1.y-cip 6/6] clk: versaclock3: Drop ret variable Biju Das
2024-02-02 11:45 ` [PATCH 6.1.y-cip 0/6] Versa3 clk driver improvements Pavel Machek
2024-02-02 12:08 ` nobuhiro1.iwamatsu
2024-02-05 11:23 ` Pavel Machek
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