From: Pavel Machek <pavel@denx.de>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Pavel Machek <pavel@denx.de>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4.19.y-cip] memory: renesas-rpc-if: Clear HS bit during hardware initialization
Date: Mon, 18 Mar 2024 12:35:50 +0100 [thread overview]
Message-ID: <ZfgnFu28JezyY23X@duo.ucw.cz> (raw)
In-Reply-To: <20240315165231.31090-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi!
> From: Cong Dang <cong.dang.xn@renesas.com>
>
> commit 5192481f908e576be42bd39ec12979b79e11f7e0 upstream.
>
> According to the datasheet, HS bit should be specified to 1 when using
> DMA transfer. As DMA transfer is not supported, it should be cleared to
> 0.
>
> Previously, the driver relied on the HS bit being cleared by prior
> firmware but this is not always the case.
>
> Fix this by ensuring the bit is cleared during hardware
> initialization.
Patch looks ok to me, I can apply it if it passes testing and if there
are no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2024-03-18 11:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-15 16:52 [PATCH 4.19.y-cip] memory: renesas-rpc-if: Clear HS bit during hardware initialization Lad Prabhakar
2024-03-18 11:35 ` Pavel Machek [this message]
2024-03-19 11:11 ` Pavel Machek
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