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From: Pavel Machek <pavel@denx.de>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de,
	cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: Re: [PATCH 5.10.y-cip 11/36] irqchip: Add RZ/G2L IA55 Interrupt Controller driver
Date: Wed, 27 Mar 2024 13:07:15 +0100	[thread overview]
Message-ID: <ZgQL8xwYwbaRdX4N@duo.ucw.cz> (raw)
In-Reply-To: <20240327081756.2228036-12-claudiu.beznea.uj@bp.renesas.com>

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Hi!

> +++ b/drivers/irqchip/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_RDA_INTC)			+= irq-rda-intc.o
>  obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
>  obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
>  obj-$(CONFIG_RENESAS_RZA1_IRQC)		+= irq-renesas-rza1.o
> +obj-$(CONFIG_RENESAS_RZG2L_IRQC)	+= irq-renesas-rzg2l.o
>  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
>  obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
>  obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> new file mode 100644
> index 000000000000..cf99cd6b41c4
> --- /dev/null
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -0,0 +1,394 @@
> +#define IRQC_IRQ_START			1
> +#define IRQC_IRQ_COUNT			8
> +#define IRQC_TINT_START			(IRQC_IRQ_START + IRQC_IRQ_COUNT)
> +#define IRQC_TINT_COUNT			32

The code hardwires assumption that interrupts are IRQ_START
.. TINT_START .. TINT_START+TINT_COUNT.

> +	raw_spin_lock(&priv->lock);
> +	if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
> +		rzg2l_irq_eoi(d);

I'd do "< IRQC_TINT_START" here.

> +static void rzg2l_irqc_irq_disable(struct irq_data *d)
> +{
> +	unsigned int hw_irq = irqd_to_hwirq(d);
> +
> +	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {

And here.

> +	if (hwirq > (IRQC_NUM_IRQ - 1))
> +		return -EINVAL;

'>= IRQC_NUM_IRQ' would be more clear here.

> +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> +{
> +	struct irq_domain *irq_domain, *parent_domain;
> +	struct platform_device *pdev;
> +	struct reset_control *resetn;
> +	struct rzg2l_irqc_priv *priv;
> +	int ret;
> +
> +	pdev = of_find_device_by_node(node);
> +	if (!pdev)
> +		return -ENODEV;
> +
> +	parent_domain = irq_find_host(parent);
> +	if (!parent_domain) {
> +		dev_err(&pdev->dev, "cannot find parent domain\n");
> +		return -ENODEV;
> +	}

I believe you'll need to put pdev in this and following error paths.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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  reply	other threads:[~2024-03-27 12:07 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-27  8:17 [PATCH 5.10.y-cip 00/36] Add IA55 interrupt controller support Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 01/36] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 02/36] pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 03/36] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 04/36] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 05/36] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 06/36] pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helper Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 07/36] pinctrl: renesas: rzg2l: Enhance driver to support interrupt affinity setting Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 08/36] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 09/36] irqdomain: Make of_phandle_args_to_fwspec() generally available Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 10/36] of: platform: Skip populating IRQ to device resource table Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 11/36] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Claudiu
2024-03-27 12:07   ` Pavel Machek [this message]
2024-03-28 11:44     ` claudiu beznea
2024-03-27  8:17 ` [PATCH 5.10.y-cip 12/36] irqchip: remove MODULE_LICENSE in non-modules Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 13/36] irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 14/36] irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 15/36] irqchip/renesas-rzg2l: Enhance driver to support interrupt affinity setting Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 16/36] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 17/36] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 18/36] irqchip/renesas-rzg2l: Document structure members Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 19/36] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 20/36] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 21/36] irqchip/renesas-rzg2l: Flush posted write in irq_eoi() Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 22/36] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 23/36] irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 24/36] irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 25/36] irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 26/36] soc: renesas: Kconfig: Enable IRQC driver for RZ/G2L SoC Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 28/36] arm64: dts: renesas: r9a07g044: " Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 29/36] arm64: dts: renesas: r9a07g054: " Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 30/36] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 31/36] arm64: dts: renesas: r9a07g044: " Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 32/36] arm64: dts: renesas: r9a07g054: " Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 33/36] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 34/36] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 35/36] arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 Claudiu
2024-03-27  8:17 ` [PATCH 5.10.y-cip 36/36] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Claudiu
2024-03-27 12:02 ` [PATCH 5.10.y-cip 00/36] Add IA55 interrupt controller support Pavel Machek
2024-03-28 10:45   ` Pavel Machek
2024-04-19 17:51 ` Krzysztof Kozlowski
2024-04-19 19:43   ` Pavel Machek
2024-04-20 11:20     ` Krzysztof Kozlowski
2024-04-21 14:11       ` Pavel Machek
2024-04-21 14:14         ` Krzysztof Kozlowski

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