Re: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[Pavel Machek <pavel@denx.de>]

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Hi!
> > Claudiu Beznea (1):
> >   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> > 
> > Lad Prabhakar (1):
> >   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> > 
> > Paul Barker (1):
> >   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
> > 
> >  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> > drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
> >  2 files changed, 15 insertions(+), 8 deletions(-)
> > 
> > 
> > base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
> 
> I reviewed this series and 5.10.y, looks good to me.
> I can apply this, if there are no other comments.
> 
> Test:
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885218
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885853
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Looks ok to me, too.

Reviewed-by: Pavel Machek <pavel@denx.de>

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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