[PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[Lad Prabhakar]

Hi All,

Fix HP clock source for RZ/Five SoC, also included
miscellaneous fixes while at it.

Note, all the patches have been cherry-picked from upstream
kernel.

Cheers,
Prabhakar


Claudiu Beznea (1):
  clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable

Lad Prabhakar (1):
  clk: renesas: r9a07g043: Fix HP clock source for RZ/Five

Paul Barker (1):
  clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const

 drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
 drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
 2 files changed, 15 insertions(+), 8 deletions(-)


base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
-- 
2.43.0

[PATCH 6.1.y-cip 1/3] clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable

[Lad Prabhakar]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit 46fb5dd9ca289953fa791b2bb060dac7f8002ae0 upstream.

Fix typo for sel_shdi variable.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240131102930.1841901-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 6 +++---
 drivers/clk/renesas/r9a07g044-cpg.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ad55a2b640aa..d3da0d10f4ed 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -90,7 +90,7 @@ static const struct clk_div_table dtable_1_32[] = {
 /* Mux clock tables */
 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
 static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
-static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
 
 static const u32 mtable_sdhi[] = { 1, 2, 3 };
 
@@ -140,9 +140,9 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
 	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
-	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
+	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
 		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
-	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_shdi,
+	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
 		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
 	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
 	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bc822b9fd7ce..48404cafea3f 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -106,7 +106,7 @@ static const struct clk_div_table dtable_16_128[] = {
 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
 static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
 static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
-static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
+static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
 
 static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -176,9 +176,9 @@ static const struct {
 		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
 		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
-		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
+		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
 			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
-		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_shdi,
+		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
 			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
 		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
 		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
-- 
2.43.0

[PATCH 6.1.y-cip 2/3] clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const

[Lad Prabhakar]

From: Paul Barker <paul.barker.ct@bp.renesas.com>

commit b8ae9d344d09b73361493054fbde15b9f5ebe91a upstream.

The r9a07g043_mod_clks and r9a07g043_resets arrays describe the module
clocks and reset signals (respectively) in this SoC and do not change at
runtime.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240320082831.9666-1-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index d3da0d10f4ed..c3c2b0c43983 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -154,7 +154,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 #endif
 };
 
-static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
+static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
 #ifdef CONFIG_ARM64
 	DEF_MOD("gic",		R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
 				0x514, 0),
@@ -297,7 +297,7 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
 #endif
 };
 
-static struct rzg2l_reset r9a07g043_resets[] = {
+static const struct rzg2l_reset r9a07g043_resets[] = {
 #ifdef CONFIG_ARM64
 	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
 	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
-- 
2.43.0

[PATCH 6.1.y-cip 3/3] clk: renesas: r9a07g043: Fix HP clock source for RZ/Five

[Lad Prabhakar]

commit 7f22a298d926664b51fcfe2f8ea5feb7f8b79952 upstream.

According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock
source for HP is derived from PLL6 divided by 2.  Correct the
implementation by configuring HP as a fixed clock source instead of a
MUX.

The `CPG_PL6_ETH_SSEL' register, which is available on the RZ/G2UL SoC,
is not present on the RZ/Five SoC, necessitating this change.

Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Cc: stable@vger.kernel.org
Reported-by: Hien Huynh <hien.huynh.px@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250127173159.34572-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g043-cpg.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index c3c2b0c43983..fce2eecfa8c0 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -89,7 +89,9 @@ static const struct clk_div_table dtable_1_32[] = {
 
 /* Mux clock tables */
 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+#ifdef CONFIG_ARM64
 static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
+#endif
 static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
 
 static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -137,7 +139,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 	DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
 	DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
 	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
+#ifdef CONFIG_ARM64
 	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
+#endif
+#ifdef CONFIG_RISCV
+	DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),
+#endif
 	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
 	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
-- 
2.43.0

RE: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[nobuhiro1.iwamatsu]

Hi,

> -----Original Message-----
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Sent: Tuesday, April 22, 2025 3:30 AM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> ＣＰＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source
> 
> Hi All,
> 
> Fix HP clock source for RZ/Five SoC, also included miscellaneous fixes while at
> it.
> 
> Note, all the patches have been cherry-picked from upstream kernel.
> 
> Cheers,
> Prabhakar
> 
> 
> Claudiu Beznea (1):
>   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> 
> Lad Prabhakar (1):
>   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> 
> Paul Barker (1):
>   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
> 
>  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
>  2 files changed, 15 insertions(+), 8 deletions(-)
> 
> 
> base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc

I reviewed this series and 5.10.y, looks good to me.
I can apply this, if there are no other comments.

Test:
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885218
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885853

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
  Nobuhiro

Re: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[Pavel Machek]

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Hi!
> > Claudiu Beznea (1):
> >   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> > 
> > Lad Prabhakar (1):
> >   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> > 
> > Paul Barker (1):
> >   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
> > 
> >  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> > drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
> >  2 files changed, 15 insertions(+), 8 deletions(-)
> > 
> > 
> > base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
> 
> I reviewed this series and 5.10.y, looks good to me.
> I can apply this, if there are no other comments.
> 
> Test:
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885218
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885853
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Looks ok to me, too.

Reviewed-by: Pavel Machek <pavel@denx.de>

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [cip-dev] [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[Pavel Machek]

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Hi!

> > > Claudiu Beznea (1):
> > >   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> > > 
> > > Lad Prabhakar (1):
> > >   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> > > 
> > > Paul Barker (1):
> > >   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
> > > 
> > >  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> > > drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
> > >  2 files changed, 15 insertions(+), 8 deletions(-)
> > > 
> > > 
> > > base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
> > 
> > I reviewed this series and 5.10.y, looks good to me.
> > I can apply this, if there are no other comments.
> > 
> > Test:
> >   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885218
> >   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885853
> > 
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
> Looks ok to me, too.

> Reviewed-by: Pavel Machek <pavel@denx.de>

Patches are okay, but we should wait for 6.12 "clk: renesas:
r9a07g043: Fix HP clock source for RZ/Five" before applying this.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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RE: [cip-dev] [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[Prabhakar Mahadev Lad]

Hi Pavel,

Thank you for the review.

> Subject: Re: [cip-dev] [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix
> clock source
> 
> Hi!
> 
> > > > Claudiu Beznea (1):
> > > >   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> > > >
> > > > Lad Prabhakar (1):
> > > >   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> > > >
> > > > Paul Barker (1):
> > > >   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as
> > > > const
> > > >
> > > >  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> > > > drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
> > > >  2 files changed, 15 insertions(+), 8 deletions(-)
> > > >
> > > >
> > > > base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
> > >
> > > I reviewed this series and 5.10.y, looks good to me.
> > > I can apply this, if there are no other comments.
> > >
> > > Test:
> > >   https://gitlab.com/cip-project/cip-kernel/linux-cip/-
> /pipelines/1778885218
> > >
> > > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778
> > > 885853
> > >
> > > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> >
> > Looks ok to me, too.
> 
> > Reviewed-by: Pavel Machek <pavel@denx.de>
> 
> Patches are okay, but we should wait for 6.12 "clk: renesas:
> r9a07g043: Fix HP clock source for RZ/Five" before applying this.
>
For 6.12 we should get this patch via stable tree, where the patch is already merged [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-6.12.y&id=56c29847bc4ca651ebeac0671f1a8519a47506e8

Cheers,
Prabhakar

RE: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source

[nobuhiro1.iwamatsu]

HI all,

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Tuesday, April 22, 2025 7:05 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Cc: prabhakar.mahadev-lad.rj@bp.renesas.com; cip-dev@lists.cip-project.org;
> biju.das.jz@bp.renesas.com
> Subject: Re: [PATCH 6.1.y-cip 0/3] clk: renesas: r9a07g043: Fix clock source
> 
> Hi!
> > > Claudiu Beznea (1):
> > >   clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable
> > >
> > > Lad Prabhakar (1):
> > >   clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
> > >
> > > Paul Barker (1):
> > >   clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
> > >
> > >  drivers/clk/renesas/r9a07g043-cpg.c | 17 ++++++++++++-----
> > > drivers/clk/renesas/r9a07g044-cpg.c |  6 +++---
> > >  2 files changed, 15 insertions(+), 8 deletions(-)
> > >
> > >
> > > base-commit: 38336ea2d1beb9af557adcc91b04e82478f539bc
> >
> > I reviewed this series and 5.10.y, looks good to me.
> > I can apply this, if there are no other comments.
> >
> > Test:
> >
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1778885218
> >
> > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/177888
> > 5853
> >
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
> Looks ok to me, too.
> 
> Reviewed-by: Pavel Machek <pavel@denx.de>
> 
Thank you, applied.

Best regards,
  Nobuhiro