From: Pavel Machek <pavel@denx.de>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Subject: Re: [PATCH 6.12.y-cip 03/10] soc: renesas: Add SYSC driver for Renesas RZ family
Date: Wed, 23 Apr 2025 21:15:43 +0200 [thread overview]
Message-ID: <aAk8X/KVkfcYJz2O@duo.ucw.cz> (raw)
In-Reply-To: <20250423181400.13960-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi!
> commit c1aca5588279fc341a2e12d61e853bb1fd4c72d5 upstream.
>
> The RZ/G3S system controller (SYSC) has various registers that control
> different functionalities. One of the exposed register offers
> information about the SoC identification.
>
> Add a driver that identifies the SoC. Later the driver will be extended
> with other functionalities.
Nitpick:
> +++ b/drivers/soc/renesas/rz-sysc.c
> +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match)
> +{
> + const struct rz_sysc_init_data *sysc_data = match->data;
> + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data;
> + struct soc_device_attribute *soc_dev_attr;
> + const char *soc_id_start, *soc_id_end;
> + u32 val, revision, specific_id;
> + struct soc_device *soc_dev;
> + char soc_id[32] = {0};
> + size_t size;
> +
> + soc_id_start = strchr(match->compatible, ',') + 1;
> + soc_id_end = strchr(match->compatible, '-');
> + size = soc_id_end - soc_id_start + 1;
> + if (size > 32)
> + size = sizeof(soc_id);
I'd expect sizeof(soc_id) instead of 32... or maybe 32 in both places,
or maybe const int max_size = 32, and then using it three times.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2025-04-23 19:15 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-23 18:13 [PATCH 6.12.y-cip 00/10] Add SYS and OPP support to Renesas RZ/V2H(P) SoC Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 01/10] clk: renesas: r9a09g057: Add reset entry for SYS Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 02/10] clk: renesas: r9a09g057: Add clock and reset entries for GIC Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 03/10] soc: renesas: Add SYSC driver for Renesas RZ family Lad Prabhakar
2025-04-23 19:15 ` Pavel Machek [this message]
2025-04-23 19:42 ` Prabhakar Mahadev Lad
2025-04-23 18:13 ` [PATCH 6.12.y-cip 04/10] soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 05/10] soc: renesas: rz-sysc: Add support for RZ/G3E family Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 06/10] soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driver Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 07/10] soc: renesas: r9a09g057-sys: Add a callback to print SoC-specific extra features Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 08/10] arm64: dts: renesas: r9a08g045: Enable SYS node Lad Prabhakar
2025-04-23 18:13 ` [PATCH 6.12.y-cip 09/10] arm64: dts: renesas: r9a09g057: " Lad Prabhakar
2025-04-23 18:14 ` [PATCH 6.12.y-cip 10/10] arm64: dts: renesas: r9a09g057: Add OPP table Lad Prabhakar
2025-04-23 19:16 ` [cip-dev] [PATCH 6.12.y-cip 00/10] Add SYS and OPP support to Renesas RZ/V2H(P) SoC Pavel Machek
2025-04-25 7:31 ` Pavel Machek
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