From: Pavel Machek <pavel@denx.de>
To: prabhakar.mahadev-lad.rj@bp.renesas.com
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [cip-dev] [PATCH 6.12.y-cip] clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
Date: Thu, 24 Apr 2025 13:10:29 +0200 [thread overview]
Message-ID: <aAocJbbP7I+9GtfP@duo.ucw.cz> (raw)
In-Reply-To: <20250422123255.7722-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi!
> commit 989d673ff7c461b2abd472227fdb7df69860d23f upstream.
>
> Add clock and reset entries for the DRP-AI block, which is available only
> on the Renesas RZ/V2L SoC.
Thank you, applied.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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prev parent reply other threads:[~2025-04-24 11:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-22 12:32 [PATCH 6.12.y-cip] clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI Lad Prabhakar
2025-04-24 11:10 ` Pavel Machek [this message]
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