* [PATCH 6.12.y-cip 1/7] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
@ 2025-06-03 9:19 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 2/7] serial: sh-sci: Update the suspend/resume support Claudiu
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:19 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit b73435047ef74c82d6e82c333810eba0038f9cf7 upstream.
The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug
console and is already enabled. Add clock, reset and power domain
support for the remaining ones.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[claudiu.beznea: fixed conflict by using RZG2L_PD_F_NONE instead of zero
to describe the power domain flags]
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/clk/renesas/r9a08g045-cpg.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 1610d4bf203f..70ad59f63d45 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -232,6 +232,11 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
+ DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1),
+ DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2),
+ DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3),
+ DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
+ DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
};
@@ -261,6 +266,11 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A08G045_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A08G045_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5),
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
@@ -343,6 +353,21 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
+ DEF_PD("scif1", R9A08G045_PD_SCIF1,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(2)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif2", R9A08G045_PD_SCIF2,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(3)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif3", R9A08G045_PD_SCIF3,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(4)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif4", R9A08G045_PD_SCIF4,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif5", R9A08G045_PD_SCIF5,
+ DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)),
+ RZG2L_PD_F_NONE),
DEF_PD("vbat", R9A08G045_PD_VBAT,
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
RZG2L_PD_F_ALWAYS_ON),
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 2/7] serial: sh-sci: Update the suspend/resume support
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
2025-06-03 9:19 ` [PATCH 6.12.y-cip 1/7] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 3/7] serial: sh-sci: Save and restore more registers Claudiu
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 22a6984c5b5df8eab864d7f3e8b94d5a554d31ab upstream.
The Renesas RZ/G3S supports a power saving mode where power to most of the
SoC components is turned off. When returning from this power saving mode,
SoC components need to be re-configured.
The SCIFs on the Renesas RZ/G3S need to be re-configured as well when
returning from this power saving mode. The sh-sci code already configures
the SCIF clocks, power domain and registers by calling uart_resume_port()
in sci_resume(). On suspend path the SCIF UART ports are suspended
accordingly (by calling uart_suspend_port() in sci_suspend()). The only
missing setting is the reset signal. For this assert/de-assert the reset
signal on driver suspend/resume.
In case the no_console_suspend is specified by the user, the registers need
to be saved on suspend path and restore on resume path. To do this the
sci_console_save()/sci_console_restore() functions were added. There is no
need to cache/restore the status or FIFO registers. Only the control
registers. The registers that will be saved/restored on suspend/resume are
specified by the struct sci_suspend_regs data structure.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250207113313.545432-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/tty/serial/sh-sci.c | 71 +++++++++++++++++++++++++++++++++++--
1 file changed, 69 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 66f78f8c4909..f0ad251d352c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -104,6 +104,15 @@ struct plat_sci_reg {
u8 offset, size;
};
+struct sci_suspend_regs {
+ u16 scsmr;
+ u16 scscr;
+ u16 scfcr;
+ u16 scsptr;
+ u8 scbrr;
+ u8 semr;
+};
+
struct sci_port_params {
const struct plat_sci_reg regs[SCIx_NR_REGS];
unsigned int fifosize;
@@ -134,6 +143,8 @@ struct sci_port {
struct dma_chan *chan_tx;
struct dma_chan *chan_rx;
+ struct reset_control *rstc;
+
#ifdef CONFIG_SERIAL_SH_SCI_DMA
struct dma_chan *chan_tx_saved;
struct dma_chan *chan_rx_saved;
@@ -153,6 +164,7 @@ struct sci_port {
int rx_trigger;
struct timer_list rx_fifo_timer;
int rx_fifo_timeout;
+ struct sci_suspend_regs suspend_regs;
u16 hscif_tot;
bool has_rtscts;
@@ -3374,6 +3386,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
}
sp = &sci_ports[id];
+ sp->rstc = rstc;
*dev_id = id;
p->type = SCI_OF_TYPE(data);
@@ -3546,13 +3559,57 @@ static int sci_probe(struct platform_device *dev)
return 0;
}
+static void sci_console_save(struct sci_port *s)
+{
+ struct sci_suspend_regs *regs = &s->suspend_regs;
+ struct uart_port *port = &s->port;
+
+ if (sci_getreg(port, SCSMR)->size)
+ regs->scsmr = sci_serial_in(port, SCSMR);
+ if (sci_getreg(port, SCSCR)->size)
+ regs->scscr = sci_serial_in(port, SCSCR);
+ if (sci_getreg(port, SCFCR)->size)
+ regs->scfcr = sci_serial_in(port, SCFCR);
+ if (sci_getreg(port, SCSPTR)->size)
+ regs->scsptr = sci_serial_in(port, SCSPTR);
+ if (sci_getreg(port, SCBRR)->size)
+ regs->scbrr = sci_serial_in(port, SCBRR);
+ if (sci_getreg(port, SEMR)->size)
+ regs->semr = sci_serial_in(port, SEMR);
+}
+
+static void sci_console_restore(struct sci_port *s)
+{
+ struct sci_suspend_regs *regs = &s->suspend_regs;
+ struct uart_port *port = &s->port;
+
+ if (sci_getreg(port, SCSMR)->size)
+ sci_serial_out(port, SCSMR, regs->scsmr);
+ if (sci_getreg(port, SCSCR)->size)
+ sci_serial_out(port, SCSCR, regs->scscr);
+ if (sci_getreg(port, SCFCR)->size)
+ sci_serial_out(port, SCFCR, regs->scfcr);
+ if (sci_getreg(port, SCSPTR)->size)
+ sci_serial_out(port, SCSPTR, regs->scsptr);
+ if (sci_getreg(port, SCBRR)->size)
+ sci_serial_out(port, SCBRR, regs->scbrr);
+ if (sci_getreg(port, SEMR)->size)
+ sci_serial_out(port, SEMR, regs->semr);
+}
+
static __maybe_unused int sci_suspend(struct device *dev)
{
struct sci_port *sport = dev_get_drvdata(dev);
- if (sport)
+ if (sport) {
uart_suspend_port(&sci_uart_driver, &sport->port);
+ if (!console_suspend_enabled && uart_console(&sport->port))
+ sci_console_save(sport);
+ else
+ return reset_control_assert(sport->rstc);
+ }
+
return 0;
}
@@ -3560,8 +3617,18 @@ static __maybe_unused int sci_resume(struct device *dev)
{
struct sci_port *sport = dev_get_drvdata(dev);
- if (sport)
+ if (sport) {
+ if (!console_suspend_enabled && uart_console(&sport->port)) {
+ sci_console_restore(sport);
+ } else {
+ int ret = reset_control_deassert(sport->rstc);
+
+ if (ret)
+ return ret;
+ }
+
uart_resume_port(&sci_uart_driver, &sport->port);
+ }
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 3/7] serial: sh-sci: Save and restore more registers
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
2025-06-03 9:19 ` [PATCH 6.12.y-cip 1/7] clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 2/7] serial: sh-sci: Update the suspend/resume support Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 4/7] arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces Claudiu
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 81100b9a7b0515132996d62a7a676a77676cb6e3 upstream.
On (H)SCIF with a Baud Rate Generator for External Clock (BRG), there
are multiple ways to configure the requested serial speed. If firmware
uses a different method than Linux, and if any debug info is printed
after the Bit Rate Register (SCBRR) is restored, but before termios is
reconfigured (which configures the alternative method), the system may
lock-up during resume.
Fix this by saving and restoring the contents of the BRG Frequency
Division (SCDL) and Clock Select (SCCKS) registers as well.
Also save and restore the HSCIF's Sampling Rate Register (HSSRR), which
configures the sampling point, and the SCIFA/SCIFB's Serial Port Control
and Data Registers (SCPCR/SCPDR), which configure the optional control
flow signals.
After this, all registers that are not saved/restored are either:
- read-only,
- write-only,
- status registers containing flags with clear-after-set semantics,
- FIFO Data Count Trigger registers, which do not matter much for
the serial console.
Fixes: 22a6984c5b5df8ea ("serial: sh-sci: Update the suspend/resume support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/11c2eab45d48211e75d8b8202cce60400880fe55.1741114989.git.geert+renesas@glider.be
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/tty/serial/sh-sci.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index f0ad251d352c..3ea1d13fe5cb 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -105,10 +105,15 @@ struct plat_sci_reg {
};
struct sci_suspend_regs {
+ u16 scdl;
+ u16 sccks;
u16 scsmr;
u16 scscr;
u16 scfcr;
u16 scsptr;
+ u16 hssrr;
+ u16 scpcr;
+ u16 scpdr;
u8 scbrr;
u8 semr;
};
@@ -3564,6 +3569,10 @@ static void sci_console_save(struct sci_port *s)
struct sci_suspend_regs *regs = &s->suspend_regs;
struct uart_port *port = &s->port;
+ if (sci_getreg(port, SCDL)->size)
+ regs->scdl = sci_serial_in(port, SCDL);
+ if (sci_getreg(port, SCCKS)->size)
+ regs->sccks = sci_serial_in(port, SCCKS);
if (sci_getreg(port, SCSMR)->size)
regs->scsmr = sci_serial_in(port, SCSMR);
if (sci_getreg(port, SCSCR)->size)
@@ -3574,6 +3583,12 @@ static void sci_console_save(struct sci_port *s)
regs->scsptr = sci_serial_in(port, SCSPTR);
if (sci_getreg(port, SCBRR)->size)
regs->scbrr = sci_serial_in(port, SCBRR);
+ if (sci_getreg(port, HSSRR)->size)
+ regs->hssrr = sci_serial_in(port, HSSRR);
+ if (sci_getreg(port, SCPCR)->size)
+ regs->scpcr = sci_serial_in(port, SCPCR);
+ if (sci_getreg(port, SCPDR)->size)
+ regs->scpdr = sci_serial_in(port, SCPDR);
if (sci_getreg(port, SEMR)->size)
regs->semr = sci_serial_in(port, SEMR);
}
@@ -3583,6 +3598,10 @@ static void sci_console_restore(struct sci_port *s)
struct sci_suspend_regs *regs = &s->suspend_regs;
struct uart_port *port = &s->port;
+ if (sci_getreg(port, SCDL)->size)
+ sci_serial_out(port, SCDL, regs->scdl);
+ if (sci_getreg(port, SCCKS)->size)
+ sci_serial_out(port, SCCKS, regs->sccks);
if (sci_getreg(port, SCSMR)->size)
sci_serial_out(port, SCSMR, regs->scsmr);
if (sci_getreg(port, SCSCR)->size)
@@ -3593,6 +3612,12 @@ static void sci_console_restore(struct sci_port *s)
sci_serial_out(port, SCSPTR, regs->scsptr);
if (sci_getreg(port, SCBRR)->size)
sci_serial_out(port, SCBRR, regs->scbrr);
+ if (sci_getreg(port, HSSRR)->size)
+ sci_serial_out(port, HSSRR, regs->hssrr);
+ if (sci_getreg(port, SCPCR)->size)
+ sci_serial_out(port, SCPCR, regs->scpcr);
+ if (sci_getreg(port, SCPDR)->size)
+ sci_serial_out(port, SCPDR, regs->scpdr);
if (sci_getreg(port, SEMR)->size)
sci_serial_out(port, SEMR, regs->semr);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 4/7] arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (2 preceding siblings ...)
2025-06-03 9:20 ` [PATCH 6.12.y-cip 3/7] serial: sh-sci: Save and restore more registers Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 5/7] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches Claudiu
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit aaf7188d7f77bb8a6e043c70dc6cc6616c427762 upstream.
The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug
console. Add the remaining ones.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241115134401.3893008-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90 ++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 7cf8587bfe0f..1707d47a09df 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -87,6 +87,96 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif5: serial@1004e000 {
+ compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+ reg = <0 0x1004e000 0 0x400>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
rtc: rtc@1004ec00 {
compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
reg = <0 0x1004ec00 0 0x400>;
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 5/7] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (3 preceding siblings ...)
2025-06-03 9:20 ` [PATCH 6.12.y-cip 4/7] arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 6/7] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Claudiu
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 02760e35b5a62f0ca24e792817d720a2c8ddd409 upstream.
There are different switches available on both the RZ/G3S SMARC Module and
RZ SMARC Carrier II boards. These switches are used to route different SoC
signals to different parts available on board.
These switches are described in device trees through macros. These macros
are set accordingly such that the resulted compiled dtb to describe the
on-board switches states.
The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches.
SCIF1 can be enabled through a device tree overlay. To manage all switches
in a unified state and allow users to configure the output device tree, add
a file that contains all switch definitions and states.
Commit prepares the code to enable SCIF1 on the RZ/G3S overlay.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +-----------
.../boot/dts/renesas/rzg3s-smarc-switches.h | 32 +++++++++++++++++++
2 files changed, 33 insertions(+), 19 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 7ae319d941ac..7c40532fc869 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -9,25 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
-/*
- * On-board switches' states:
- * @SW_OFF: switch's state is OFF
- * @SW_ON: switch's state is ON
- */
-#define SW_OFF 0
-#define SW_ON 1
-
-/*
- * SW_CONFIG[x] switches' states:
- * @SW_CONFIG2:
- * SW_OFF - SD0 is connected to eMMC
- * SW_ON - SD0 is connected to uSD0 card
- * @SW_CONFIG3:
- * SW_OFF - SD2 is connected to SoC
- * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
- */
-#define SW_CONFIG2 SW_OFF
-#define SW_CONFIG3 SW_ON
+#include "rzg3s-smarc-switches.h"
/ {
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
new file mode 100644
index 000000000000..5c27c043afef
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II
+ * boards.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#ifndef __RZG3S_SMARC_SWITCHES_H__
+#define __RZG3S_SMARC_SWITCHES_H__
+
+/*
+ * On-board switches' states:
+ * @SW_OFF: switch's state is OFF
+ * @SW_ON: switch's state is ON
+ */
+#define SW_OFF 0
+#define SW_ON 1
+
+/*
+ * SW_CONFIG[x] switches' states:
+ * @SW_CONFIG2:
+ * SW_OFF - SD0 is connected to eMMC
+ * SW_ON - SD0 is connected to uSD0 card
+ * @SW_CONFIG3:
+ * SW_OFF - SD2 is connected to SoC
+ * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
+ */
+#define SW_CONFIG2 SW_OFF
+#define SW_CONFIG3 SW_ON
+
+#endif /* __RZG3S_SMARC_SWITCHES_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 6/7] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (4 preceding siblings ...)
2025-06-03 9:20 ` [PATCH 6.12.y-cip 5/7] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:20 ` [PATCH 6.12.y-cip 7/7] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 Claudiu
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit ec32d57b4bbf27d91c55c7a258bdb87690993ea6 upstream.
Enable SCIF3. It is routed to the SER1_UART interface on the RZ SMARC
Carrier II board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 3c810db81861..34adfbf2ec76 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
i2c0 = &i2c0;
+ serial1 = &scif3;
serial3 = &scif0;
mmc1 = &sdhi1;
};
@@ -152,6 +153,11 @@ scif0_pins: scif0 {
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};
+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */
+ <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */
+ };
+
sdhi1_pins: sd1 {
data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
@@ -198,6 +204,12 @@ &scif0 {
status = "okay";
};
+&scif3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif3_pins>;
+ status = "okay";
+};
+
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.12.y-cip 7/7] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (5 preceding siblings ...)
2025-06-03 9:20 ` [PATCH 6.12.y-cip 6/7] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Claudiu
@ 2025-06-03 9:20 ` Claudiu
2025-06-03 9:40 ` [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Pavel Machek
2025-06-04 6:17 ` nobuhiro1.iwamatsu
8 siblings, 0 replies; 11+ messages in thread
From: Claudiu @ 2025-06-03 9:20 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit cc018b98a9bf47c06bc985632a7ed9291decb965 upstream.
Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through
the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II
board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 3 ++
.../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 +++++++++++++++++++
.../boot/dts/renesas/rzg3s-smarc-switches.h | 8 ++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 1 +
4 files changed, 60 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index bf5b49f47ce8..7959f62a8e26 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -137,6 +137,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
+r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
+dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
new file mode 100644
index 000000000000..4a81e3a3c8bd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ *
+ * [Connection]
+ *
+ * SMARC Carrier II EVK
+ * +--------------------------------------------+
+ * |PMOD1_3A (PMOD1 PIN HEADER) |
+ * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 |
+ * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 |
+ * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 |
+ * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 |
+ * | GND (pin5) (pin11) GND |
+ * | PWR_PMOD1 (pin6) (pin12) GND |
+ * +--------------------------------------------+
+ *
+ * The following switches should be set as follows for SCIF1:
+ * - SW_CONFIG2: ON
+ * - SW_OPT_MUX4: ON
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include "rzg3s-smarc-switches.h"
+
+&pinctrl {
+ scif1_pins: scif1-pins {
+ pinmux = <RZG2L_PORT_PINMUX(14, 0, 1)>, /* TXD */
+ <RZG2L_PORT_PINMUX(14, 1, 1)>, /* RXD */
+ <RZG2L_PORT_PINMUX(16, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS# */
+ };
+};
+
+#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON
+&scif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif1_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+#endif
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
index 5c27c043afef..bbf908a5322c 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
@@ -29,4 +29,12 @@
#define SW_CONFIG2 SW_OFF
#define SW_CONFIG3 SW_ON
+/*
+ * SW_OPT_MUX[x] switches' states:
+ * @SW_OPT_MUX4:
+ * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART
+ * SW_ON - The SMARC SER0 signals are routed to PMOD1
+ */
+#define SW_OPT_MUX4 SW_ON
+
#endif /* __RZG3S_SMARC_SWITCHES_H__ */
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index 34adfbf2ec76..db05c28a8f6c 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
i2c0 = &i2c0;
+ serial0 = &scif1;
serial1 = &scif3;
serial3 = &scif0;
mmc1 = &sdhi1;
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (6 preceding siblings ...)
2025-06-03 9:20 ` [PATCH 6.12.y-cip 7/7] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 Claudiu
@ 2025-06-03 9:40 ` Pavel Machek
2025-06-04 6:17 ` nobuhiro1.iwamatsu
8 siblings, 0 replies; 11+ messages in thread
From: Pavel Machek @ 2025-06-03 9:40 UTC (permalink / raw)
To: Claudiu; +Cc: nobuhiro1.iwamatsu, cip-dev
[-- Attachment #1: Type: text/plain, Size: 407 bytes --]
Hi!
> Series backports the Renesas RZ/G3S SCIF support to v6.12.y CIP.
Looks good to me. I can apply it provided it passes testing and there
are no other comments.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* RE: [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support
2025-06-03 9:19 [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Claudiu
` (7 preceding siblings ...)
2025-06-03 9:40 ` [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support Pavel Machek
@ 2025-06-04 6:17 ` nobuhiro1.iwamatsu
2025-06-04 18:12 ` Pavel Machek
8 siblings, 1 reply; 11+ messages in thread
From: nobuhiro1.iwamatsu @ 2025-06-04 6:17 UTC (permalink / raw)
To: claudiu.beznea, pavel; +Cc: cip-dev
Hi,
> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Tuesday, June 3, 2025 6:20 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro1.iwamatsu@toshiba.co.jp>; pavel@denx.de
> Cc: claudiu.beznea@tuxon.dev; cip-dev@lists.cip-project.org
> Subject: [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support
>
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Hi,
>
> Series backports the Renesas RZ/G3S SCIF support to v6.12.y CIP.
>
> Thank you,
> Claudiu Beznea
>
> Claudiu Beznea (6):
> clk: renesas: r9a08g045: Add clock, reset and power domain for the
> remaining SCIFs
> serial: sh-sci: Update the suspend/resume support
> arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces
> arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe
> different switches
> arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
> arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
>
> Geert Uytterhoeven (1):
> serial: sh-sci: Save and restore more registers
>
> arch/arm64/boot/dts/renesas/Makefile | 3 +
> arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90
> +++++++++++++++++
> .../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 ++++++++++
> .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +---
> .../boot/dts/renesas/rzg3s-smarc-switches.h | 40 ++++++++
> arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 13 +++
> drivers/clk/renesas/r9a08g045-cpg.c | 25 +++++
> drivers/tty/serial/sh-sci.c | 96
> ++++++++++++++++++-
> 8 files changed, 314 insertions(+), 21 deletions(-) create mode 100644
> arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
> create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
I reviewed this series, looks good to me.
I can apply these, if there are no other comments.
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Test:
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1852365220
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 6.12.y-cip 0/7] RZ/G3S: Backport SCIF support
2025-06-04 6:17 ` nobuhiro1.iwamatsu
@ 2025-06-04 18:12 ` Pavel Machek
0 siblings, 0 replies; 11+ messages in thread
From: Pavel Machek @ 2025-06-04 18:12 UTC (permalink / raw)
To: nobuhiro1.iwamatsu; +Cc: claudiu.beznea, cip-dev
[-- Attachment #1: Type: text/plain, Size: 1895 bytes --]
Hi!
> > Series backports the Renesas RZ/G3S SCIF support to v6.12.y CIP.
> >
> > Thank you,
> > Claudiu Beznea
> >
> > Claudiu Beznea (6):
> > clk: renesas: r9a08g045: Add clock, reset and power domain for the
> > remaining SCIFs
> > serial: sh-sci: Update the suspend/resume support
> > arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces
> > arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe
> > different switches
> > arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
> > arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
> >
> > Geert Uytterhoeven (1):
> > serial: sh-sci: Save and restore more registers
> >
> > arch/arm64/boot/dts/renesas/Makefile | 3 +
> > arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90
> > +++++++++++++++++
> > .../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 ++++++++++
> > .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +---
> > .../boot/dts/renesas/rzg3s-smarc-switches.h | 40 ++++++++
> > arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 13 +++
> > drivers/clk/renesas/r9a08g045-cpg.c | 25 +++++
> > drivers/tty/serial/sh-sci.c | 96
> > ++++++++++++++++++-
> > 8 files changed, 314 insertions(+), 21 deletions(-) create mode 100644
> > arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso
> > create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h
>
> I reviewed this series, looks good to me.
> I can apply these, if there are no other comments.
>
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Thank you, I added your reviewed-by tag and applied the series.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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