[PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[Tommaso Merciai]

Hi All,

This patch series aims to add Watchdog Timer (WDT) support for the
Renesas RZ/G3E SoCs.

The RZ/G3E WDT IP is similar to RZ/V2H WDT. WDT0 can be used for CM33 cold
reset, system reset and asserting WDTUDFCM pin where as WDT1 can be used
for CA55 cold reset, system reset and asserting WDTUDFCA pin. Other 2
watchdogs can be used for system reset. So define WDT{1..3} in SoC dtsi.

Thanks & Regards,
Tommaso

Biju Das (5):
  clk: renesas: r9a09g047: Add WDT clocks and resets
  dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support
  watchdog: Enable RZV2HWDT driver depend on ARCH_RENESAS
  arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
  arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog

Lad Prabhakar (2):
  watchdog: rzv2h_wdt: Use local `dev` pointer in probe
  arm64: defconfig: Enable Renesas RZ/V2H(P) Watchdog driver

 .../bindings/watchdog/renesas,wdt.yaml        |  4 +++
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 30 +++++++++++++++++++
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  4 +++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/clk/renesas/r9a09g047-cpg.c           | 15 ++++++++++
 drivers/watchdog/Kconfig                      |  7 +++--
 drivers/watchdog/rzv2h_wdt.c                  | 16 +++++-----
 7 files changed, 66 insertions(+), 11 deletions(-)

-- 
2.43.0

[PATCH 6.12.y-cip 1/7] clk: renesas: r9a09g047: Add WDT clocks and resets

[Tommaso Merciai]

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 3c437d906f997a4e1495f59773b9a2544fff69ce upstream.

WDT0 reset is for CM33.  Add WDT[1-3] clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 536d922bed70..1886eab9ef9e 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -92,6 +92,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
 						BUS_MSTOP(3, BIT(5))),
+	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
+						BUS_MSTOP(1, BIT(0))),
+	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
+						BUS_MSTOP(1, BIT(0))),
+	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,
+						BUS_MSTOP(5, BIT(12))),
+	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,
+						BUS_MSTOP(5, BIT(12))),
+	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
+						BUS_MSTOP(5, BIT(13))),
+	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
+						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
 						BUS_MSTOP(3, BIT(14))),
 	DEF_MOD("riic_8_ckm",			CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -118,6 +130,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
+	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
+	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
+	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
 	DEF_RST(9, 8, 4, 9),		/* RIIC_0_MRST */
 	DEF_RST(9, 9, 4, 10),		/* RIIC_1_MRST */
-- 
2.43.0

[PATCH 6.12.y-cip 2/7] dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support

[Tommaso Merciai]

From: Biju Das <biju.das.jz@bp.renesas.com>

commit c40524d1615a72548adc30dbfb15c981fd03dacb upstream.

Document the support for the watchdog IP available on RZ/G3E SoC. The
watchdog IP available on RZ/G3E SoC is identical to the one found on
RZ/V2H SoC.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250126132633.31956-2-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
index 29ada89fdcdc..3e0a8747a357 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
@@ -75,6 +75,10 @@ properties:
               - renesas,r8a779h0-wdt     # R-Car V4M
           - const: renesas,rcar-gen4-wdt # R-Car Gen4
 
+      - items:
+          - const: renesas,r9a09g047-wdt # RZ/G3E
+          - const: renesas,r9a09g057-wdt # RZ/V2H(P)
+
       - const: renesas,r9a09g057-wdt       # RZ/V2H(P)
 
   reg:
-- 
2.43.0

[PATCH 6.12.y-cip 3/7] watchdog: rzv2h_wdt: Use local `dev` pointer in probe

[Tommaso Merciai]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 1f2b24a524fc20a7e893981c1a2e12d080e90ee6 upstream.

Update the `rzv2h_wdt_probe()` function to consistently use the local
`dev` pointer, which is already extracted from `&pdev->dev`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20241213171157.898934-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/watchdog/rzv2h_wdt.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index 1d1b17312747..8defd0241213 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -217,24 +217,24 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
 
-	priv->pclk = devm_clk_get_prepared(&pdev->dev, "pclk");
+	priv->pclk = devm_clk_get_prepared(dev, "pclk");
 	if (IS_ERR(priv->pclk))
-		return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
+		return dev_err_probe(dev, PTR_ERR(priv->pclk), "no pclk");
 
-	priv->oscclk = devm_clk_get_prepared(&pdev->dev, "oscclk");
+	priv->oscclk = devm_clk_get_prepared(dev, "oscclk");
 	if (IS_ERR(priv->oscclk))
-		return dev_err_probe(&pdev->dev, PTR_ERR(priv->oscclk), "no oscclk");
+		return dev_err_probe(dev, PTR_ERR(priv->oscclk), "no oscclk");
 
-	priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	priv->rstc = devm_reset_control_get_exclusive(dev, NULL);
 	if (IS_ERR(priv->rstc))
-		return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
+		return dev_err_probe(dev, PTR_ERR(priv->rstc),
 				     "failed to get cpg reset");
 
 	priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256) /
 					 clk_get_rate(priv->oscclk);
 	dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
 
-	ret = devm_pm_runtime_enable(&pdev->dev);
+	ret = devm_pm_runtime_enable(dev);
 	if (ret)
 		return ret;
 
@@ -251,7 +251,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 	if (ret)
 		dev_warn(dev, "Specified timeout invalid, using default");
 
-	return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
+	return devm_watchdog_register_device(dev, &priv->wdev);
 }
 
 static const struct of_device_id rzv2h_wdt_ids[] = {
-- 
2.43.0

[PATCH 6.12.y-cip 4/7] watchdog: Enable RZV2HWDT driver depend on ARCH_RENESAS

[Tommaso Merciai]

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 331c8349605c8fa2f9040c39fe8c40afe3fdc3c3 upstream.

RZ/G3E watchdog timer IP is similar to the one found on RZ/V2H. Both these
SoCs belong to the ARCH_RENESAS family. So, it makes sense to use
ARCH_RENESAS rather than ARCH_R9A09G057 to enable the RZV2HWDT driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20250126132633.31956-3-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/watchdog/Kconfig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0b59c669c26d..bb36b3a7727e 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -955,13 +955,14 @@ config RENESAS_RZG2LWDT
 	  Renesas RZ/G2L SoCs. These watchdogs can be used to reset a system.
 
 config RENESAS_RZV2HWDT
-	tristate "Renesas RZ/V2H(P) WDT Watchdog"
-	depends on ARCH_R9A09G057 || COMPILE_TEST
+	tristate "Renesas RZ/{G3E,V2H(P)} WDT Watchdog"
+	depends on ARCH_RENESAS || COMPILE_TEST
 	depends on PM || COMPILE_TEST
 	select WATCHDOG_CORE
 	help
 	  This driver adds watchdog support for the integrated watchdogs in the
-	  Renesas RZ/V2H(P) SoCs. These watchdogs can be used to reset a system.
+	  Renesas RZ/{G3E,V2H(P)} SoCs. These watchdogs can be used to reset a
+	  system.
 
 config ASPEED_WATCHDOG
 	tristate "Aspeed BMC watchdog support"
-- 
2.43.0

[PATCH 6.12.y-cip 5/7] arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes

[Tommaso Merciai]

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 146a9b058ec780581f580b0de9bbc0264b59d701 upstream.

Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 200e9ea89193..133aa3272d3a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -175,6 +175,36 @@ scif0: serial@11c01400 {
 			status = "disabled";
 		};
 
+		wdt1: watchdog@14400000 {
+			compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x14400000 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x76>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@13000000 {
+			compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x13000000 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x77>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@13000400 {
+			compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x13000400 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x78>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@14400400 {
 			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
 			reg = <0 0x14400400 0 0x400>;
-- 
2.43.0

[PATCH 6.12.y-cip 6/7] arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog

[Tommaso Merciai]

From: Biju Das <biju.das.jz@bp.renesas.com>

commit db2bbe1e6c48f03ed1f5ac57f5614d02351dcb4c upstream.

Enable WDT1 watchdog on RZ/G3E SMARC SoM platform.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 6b583ae2ac52..f4ba050beb0d 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -26,3 +26,7 @@ &qextal_clk {
 &rtxin_clk {
 	clock-frequency = <32768>;
 };
+
+&wdt1 {
+	status = "okay";
+};
-- 
2.43.0

[PATCH 6.12.y-cip 7/7] arm64: defconfig: Enable Renesas RZ/V2H(P) Watchdog driver

[Tommaso Merciai]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 5ad0a0c7917dc434ee28da765186dabc81172e3c upstream.

Enable the watchdog driver for the Renesas RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241112093412.20093-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4eddb85c1211..5f3d7acedad4 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -736,6 +736,7 @@ CONFIG_MESON_WATCHDOG=m
 CONFIG_ARM_SMC_WATCHDOG=y
 CONFIG_RENESAS_WDT=y
 CONFIG_RENESAS_RZG2LWDT=y
+CONFIG_RENESAS_RZV2HWDT=y
 CONFIG_UNIPHIER_WATCHDOG=y
 CONFIG_PM8916_WATCHDOG=m
 CONFIG_BCM2835_WDT=y
-- 
2.43.0

Re: [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 726 bytes --]

Hi!

> This patch series aims to add Watchdog Timer (WDT) support for the
> Renesas RZ/G3E SoCs.
> 
> The RZ/G3E WDT IP is similar to RZ/V2H WDT. WDT0 can be used for CM33 cold
> reset, system reset and asserting WDTUDFCM pin where as WDT1 can be used
> for CA55 cold reset, system reset and asserting WDTUDFCA pin. Other 2
> watchdogs can be used for system reset. So define WDT{1..3} in SoC
> dtsi.

Looks good to me. I can	apply it if it passes testing and there	are no
other comments.

Reviewed-by: Pavel Machek <pavel@denx.de>

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

Re: [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[Tommaso Merciai]

Hi Pavel,

On Mon, Jun 23, 2025 at 01:10:57PM +0200, Pavel Machek wrote:
> Hi!
> 
> > This patch series aims to add Watchdog Timer (WDT) support for the
> > Renesas RZ/G3E SoCs.
> > 
> > The RZ/G3E WDT IP is similar to RZ/V2H WDT. WDT0 can be used for CM33 cold
> > reset, system reset and asserting WDTUDFCM pin where as WDT1 can be used
> > for CA55 cold reset, system reset and asserting WDTUDFCA pin. Other 2
> > watchdogs can be used for system reset. So define WDT{1..3} in SoC
> > dtsi.
> 
> Looks good to me. I can	apply it if it passes testing and there	are no
> other comments.
> 
> Reviewed-by: Pavel Machek <pavel@denx.de>

Thanks for your work!

Regards,
Tommaso

> 
> Best regards,
> 								Pavel
> -- 
> DENX Software Engineering GmbH,        Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

RE: [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[nobuhiro1.iwamatsu]

Hi all,

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Sent: Monday, June 23, 2025 7:29 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> ＣＰＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; tomm.merciai@gmail.com
> Subject: [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT
> 
> Hi All,
> 
> This patch series aims to add Watchdog Timer (WDT) support for the Renesas
> RZ/G3E SoCs.
> 
> The RZ/G3E WDT IP is similar to RZ/V2H WDT. WDT0 can be used for CM33
> cold reset, system reset and asserting WDTUDFCM pin where as WDT1 can be
> used for CA55 cold reset, system reset and asserting WDTUDFCA pin. Other 2
> watchdogs can be used for system reset. So define WDT{1..3} in SoC dtsi.
> 
> Thanks & Regards,
> Tommaso
> 
> Biju Das (5):
>   clk: renesas: r9a09g047: Add WDT clocks and resets
>   dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support
>   watchdog: Enable RZV2HWDT driver depend on ARCH_RENESAS
>   arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
>   arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog
> 
> Lad Prabhakar (2):
>   watchdog: rzv2h_wdt: Use local `dev` pointer in probe
>   arm64: defconfig: Enable Renesas RZ/V2H(P) Watchdog driver
> 
>  .../bindings/watchdog/renesas,wdt.yaml        |  4 +++
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 30
> +++++++++++++++++++
>  .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  4 +++
>  arch/arm64/configs/defconfig                  |  1 +
>  drivers/clk/renesas/r9a09g047-cpg.c           | 15 ++++++++++
>  drivers/watchdog/Kconfig                      |  7 +++--
>  drivers/watchdog/rzv2h_wdt.c                  | 16 +++++-----
>  7 files changed, 66 insertions(+), 11 deletions(-)

I reviewed this series, looks good to me.
I can apply, if there are no other comments.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
  Nobuhiro

RE: [cip-dev] [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT

[nobuhiro1.iwamatsu]

Hi all,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
> Behalf Of Nobuhiro Iwamatsu via lists.cip-project.org
> Sent: Tuesday, June 24, 2025 1:10 PM
> To: tommaso.merciai.xr@bp.renesas.com; cip-dev@lists.cip-project.org;
> pavel@denx.de
> Cc: biju.das.jz@bp.renesas.com; prabhakar.mahadev-lad.rj@bp.renesas.com;
> tomm.merciai@gmail.com
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT
> 
> Hi all,
> 
> > -----Original Message-----
> > From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > Sent: Monday, June 23, 2025 7:29 PM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> > ＣＰＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>; tomm.merciai@gmail.com
> > Subject: [PATCH 6.12.y-cip 0/7] Add support for RZ/G3E WDT
> >
> > Hi All,
> >
> > This patch series aims to add Watchdog Timer (WDT) support for the
> > Renesas RZ/G3E SoCs.
> >
> > The RZ/G3E WDT IP is similar to RZ/V2H WDT. WDT0 can be used for CM33
> > cold reset, system reset and asserting WDTUDFCM pin where as WDT1 can
> > be used for CA55 cold reset, system reset and asserting WDTUDFCA pin.
> > Other 2 watchdogs can be used for system reset. So define WDT{1..3} in SoC
> dtsi.
> >
> > Thanks & Regards,
> > Tommaso
> >
> > Biju Das (5):
> >   clk: renesas: r9a09g047: Add WDT clocks and resets
> >   dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support
> >   watchdog: Enable RZV2HWDT driver depend on ARCH_RENESAS
> >   arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
> >   arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog
> >
> > Lad Prabhakar (2):
> >   watchdog: rzv2h_wdt: Use local `dev` pointer in probe
> >   arm64: defconfig: Enable Renesas RZ/V2H(P) Watchdog driver
> >
> >  .../bindings/watchdog/renesas,wdt.yaml        |  4 +++
> >  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 30
> > +++++++++++++++++++
> >  .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  4 +++
> >  arch/arm64/configs/defconfig                  |  1 +
> >  drivers/clk/renesas/r9a09g047-cpg.c           | 15 ++++++++++
> >  drivers/watchdog/Kconfig                      |  7 +++--
> >  drivers/watchdog/rzv2h_wdt.c                  | 16 +++++-----
> >  7 files changed, 66 insertions(+), 11 deletions(-)
> 
> I reviewed this series, looks good to me.
> I can apply, if there are no other comments.
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> 
I applied with Pavel's Reviewed-by tag.

Best regards,
  Nobuhiro