[PATCH 6.1.y-cip 16/17] arm64: dts: renesas: rzg3e-smarc-som: Add support to enable SD on SDHI0

Tommaso Merciai
2025-06-23T14:48:02Z

From: Biju Das <biju.das.jz@bp.renesas.com>

commit 4c85281bed1732693f2f2e32cf60e0e30722d06e upstream.

Add support for enabling SD on SDHI0 on RZ/G3E SMARC SoM. It is enabled
by setting the macro SW_SD0_DEV_SEL to 1 in board DTS and setting the
switch SYS.1 to ON position on the SoM.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250206134047.67866-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 3 ++
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 54 +++++++++++++++++++
2 files changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index c063d47e2952..152a00aa354b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -7,6 +7,9 @@

/dts-v1/;

+/* Switch selection settings */
+#define SW_SD0_DEV_SEL 0
+
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
#include "r9a09g047e57.dtsi"
#include "rzg3e-smarc-som.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index fcbabe2cb003..72b42a81bcf3 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -5,6 +5,15 @@
* Copyright (C) 2024 Renesas Electronics Corp.
*/

+/*
+ * Please set the switch position SYS.1 on the SoM and the corresponding macro
+ * SW_SD0_DEV_SEL on the board DTS:
+ *
+ * SW_SD0_DEV_SEL:
+ * 0 - SD0 is connected to eMMC (default)
+ * 1 - SD0 is connected to uSD0 card
+ */
+
/ {
compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";

@@ -61,6 +70,32 @@ sd0-rst {
};
};

+ sdhi0_usd_pins: sd0-usd {
+ sd0-cd {
+ pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
+ };
+
+ sd0-ctrl {
+ pins = "SD0CLK", "SD0CMD";
+ renesas,output-impedance = <3>;
+ };
+
+ sd0-data {
+ pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
+ renesas,output-impedance = <3>;
+ };
+
+ sd0-iovs {
+ pins = "SD0IOVS";
+ renesas,output-impedance = <3>;
+ };
+
+ sd0-pwen {
+ pins = "SD0PWEN";
+ renesas,output-impedance = <3>;
+ };
+ };
+
sdhi2_pins: sd2 {
sd2-cd {
pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
@@ -96,6 +131,24 @@ &rtxin_clk {
clock-frequency = <32768>;
};

+#if (SW_SD0_DEV_SEL)
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_usd_pins>;
+ pinctrl-1 = <&sdhi0_usd_pins>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&sdhi0_vqmmc>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi0_vqmmc {
+ status = "okay";
+};
+#else
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
@@ -109,6 +162,7 @@ &sdhi0 {
fixed-emmc-driver-type = <1>;
status = "okay";
};
+#endif

&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
--
2.43.0