* [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-04 12:43 ` Pavel Machek
2025-11-06 11:55 ` Pavel Machek
2025-11-03 11:37 ` [PATCH 6.12.y-cip 02/22] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC John Madieu
` (22 subsequent siblings)
23 siblings, 2 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 31d358e611b7cc21349da58dd2c9118c84b0859f ]
Add a new Kconfig option, ARCH_R9A09G056, to enable ARM64 platform support
for the Renesas RZ/V2N SoC. Default this option to "y" when ARCH_RENESAS is
enabled, ensuring that support for the RZ/V2N SoC is automatically included.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/soc/renesas/Kconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 49648cf28bd2..c679a6e089b1 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -352,6 +352,12 @@ config ARCH_R9A09G047
help
This enables support for the Renesas RZ/G3E SoC variants.
+config ARCH_R9A09G056
+ bool "ARM64 Platform support for RZ/V2N"
+ default y if ARCH_RENESAS
+ help
+ This enables support for the Renesas RZ/V2N SoC variants.
+
config ARCH_R9A09G057
bool "ARM64 Platform support for RZ/V2H(P)"
select RENESAS_RZV2H_ICU
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
2025-11-03 11:37 ` [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC John Madieu
@ 2025-11-04 12:43 ` Pavel Machek
2025-11-06 11:55 ` Pavel Machek
1 sibling, 0 replies; 33+ messages in thread
From: Pavel Machek @ 2025-11-04 12:43 UTC (permalink / raw)
To: John Madieu; +Cc: cip-dev, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 1025 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> [ Upstream commit 31d358e611b7cc21349da58dd2c9118c84b0859f ]
>
> Add a new Kconfig option, ARCH_R9A09G056, to enable ARM64 platform support
> for the Renesas RZ/V2N SoC. Default this option to "y" when
> ARCH_RENESAS is
I wonder if this one should be last in the series? We don't want to
offer option that does not work.
Best regards,
Pavel
> +++ b/drivers/soc/renesas/Kconfig
> @@ -352,6 +352,12 @@ config ARCH_R9A09G047
> help
> This enables support for the Renesas RZ/G3E SoC variants.
>
> +config ARCH_R9A09G056
> + bool "ARM64 Platform support for RZ/V2N"
> + default y if ARCH_RENESAS
> + help
> + This enables support for the Renesas RZ/V2N SoC variants.
> +
> config ARCH_R9A09G057
> bool "ARM64 Platform support for RZ/V2H(P)"
> select RENESAS_RZV2H_ICU
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
2025-11-03 11:37 ` [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC John Madieu
2025-11-04 12:43 ` Pavel Machek
@ 2025-11-06 11:55 ` Pavel Machek
1 sibling, 0 replies; 33+ messages in thread
From: Pavel Machek @ 2025-11-06 11:55 UTC (permalink / raw)
To: John Madieu; +Cc: cip-dev, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 624 bytes --]
Hi1
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> [ Upstream commit 31d358e611b7cc21349da58dd2c9118c84b0859f ]
>
> Add a new Kconfig option, ARCH_R9A09G056, to enable ARM64 platform support
> for the Renesas RZ/V2N SoC. Default this option to "y" when ARCH_RENESAS is
> enabled, ensuring that support for the RZ/V2N SoC is automatically
> included.
As for the 6.12 series, I propose to drop this patch and apply the
series.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 6.12.y-cip 02/22] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 03/22] pinctrl: renesas: rzg2l: Add support for " John Madieu
` (21 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 626acded47269bd0aae73e80a0448256924e3bf8 ]
Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.
To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 11e22610125d..0cd00eb436dc 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -27,6 +27,7 @@ properties:
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
- renesas,r9a09g047-pinctrl # RZ/G3E
+ - renesas,r9a09g056-pinctrl # RZ/V2N
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
@@ -159,6 +160,7 @@ allOf:
contains:
enum:
- renesas,r9a09g047-pinctrl
+ - renesas,r9a09g056-pinctrl
- renesas,r9a09g057-pinctrl
then:
properties:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 03/22] pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 02/22] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 04/22] pinctrl: renesas: rzg2l: Parameterize OEN register offset John Madieu
` (20 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 5488aa013e9ef17c4c7aa8c4e6166dd89c69c3c6 ]
Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing
RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with
the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N.
To handle this, the rzv2h_dedicated_pins array is refactored into a common
and pcie1 subset. This enables reuse of the common portion across both
SoCs, while excluding PCIE1_RSTOUTB for RZ/V2N.
This change allows the pinctrl-rzg2l driver to support RZ/V2N without
duplicating large parts of the RZ/V2H configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250415130854.242227-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/Kconfig | 1 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 299 +++++++++++++-----------
2 files changed, 170 insertions(+), 130 deletions(-)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 3c18d908b21e..e16034fc1bbf 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -42,6 +42,7 @@ config PINCTRL_RENESAS
select PINCTRL_RZG2L if ARCH_RZG2L
select PINCTRL_RZV2M if ARCH_R9A09G011
select PINCTRL_RZG2L if ARCH_R9A09G047
+ select PINCTRL_RZG2L if ARCH_R9A09G056
select PINCTRL_RZG2L if ARCH_R9A09G057
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 355b234ba06c..0021ca1cc988 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2230,135 +2230,146 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
PIN_CFG_IO_VMC_SD1)) },
};
-static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
- { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
- { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN)) },
- { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_NOD)) },
- { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_NOD)) },
- { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
- { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
- { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
- { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
- { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
- { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
- { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
- { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
- { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
- { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
- { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
- { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
- { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
- { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_IEN | PIN_CFG_PUPD)) },
- { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
- { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+static const struct {
+ struct rzg2l_dedicated_configs common[77];
+ struct rzg2l_dedicated_configs pcie1[1];
+} rzv2h_dedicated_pins = {
+ .common = {
+ { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
+ { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN)) },
+ { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_NOD)) },
+ { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
+ { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
+ { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
+ { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
+ { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H |
+ PIN_CFG_SR)) },
+ { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
PIN_CFG_PUPD)) },
- { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
- { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
- { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD | PIN_CFG_OEN)) },
- { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
- { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
- { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
- PIN_CFG_PUPD)) },
- { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
- { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
- { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
- { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
+ { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
+ { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H |
+ PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
+ { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
+ { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
+ { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
+ { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
+ { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
+ { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
+ { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
+ { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_IEN | PIN_CFG_PUPD)) },
+ { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
+ { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H |
+ PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
+ { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
+ { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD | PIN_CFG_OEN)) },
+ { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
+ { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
+ { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
+ PIN_CFG_PUPD)) },
+ { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
+ { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
+ { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
+ { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
+ },
+ .pcie1 = {
+ { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H |
+ PIN_CFG_SR)) },
+ },
};
static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
@@ -3349,13 +3360,37 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
+static struct rzg2l_pinctrl_data r9a09g056_data = {
+ .port_pins = rzv2h_gpio_names,
+ .port_pin_configs = r9a09g057_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
+ .dedicated_pins = rzv2h_dedicated_pins.common,
+ .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common),
+ .hwcfg = &rzv2h_hwcfg,
+ .variable_pin_cfg = r9a09g057_variable_pin_cfg,
+ .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
+ .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
+ .custom_params = renesas_rzv2h_custom_bindings,
+#ifdef CONFIG_DEBUG_FS
+ .custom_conf_items = renesas_rzv2h_conf_items,
+#endif
+ .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
+ .pmc_writeb = &rzv2h_pmc_writeb,
+ .oen_read = &rzv2h_oen_read,
+ .oen_write = &rzv2h_oen_write,
+ .hw_to_bias_param = &rzv2h_hw_to_bias_param,
+ .bias_param_to_hw = &rzv2h_bias_param_to_hw,
+};
+
static struct rzg2l_pinctrl_data r9a09g057_data = {
.port_pins = rzv2h_gpio_names,
.port_pin_configs = r9a09g057_gpio_configs,
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
- .dedicated_pins = rzv2h_dedicated_pins,
+ .dedicated_pins = rzv2h_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
- .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
+ .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) +
+ ARRAY_SIZE(rzv2h_dedicated_pins.pcie1),
.hwcfg = &rzv2h_hwcfg,
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
@@ -3389,6 +3424,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
.compatible = "renesas,r9a09g047-pinctrl",
.data = &r9a09g047_data,
},
+ {
+ .compatible = "renesas,r9a09g056-pinctrl",
+ .data = &r9a09g056_data,
+ },
{
.compatible = "renesas,r9a09g057-pinctrl",
.data = &r9a09g057_data,
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 04/22] pinctrl: renesas: rzg2l: Parameterize OEN register offset
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (2 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 03/22] pinctrl: renesas: rzg2l: Add support for " John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 05/22] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable John Madieu
` (19 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 27c76cc93c6c2ee6c0d7fec6dedc1214a977e66f ]
Prepare for supporting SoCs with varying OEN register locations by
parameterizing the OEN offset in the rzg2l driver. Introduce an `oen`
field in the rzg2l_register_offsets structure and update rzg2l_read_oen(),
rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use
this offset instead of the hard-coded ETH_MODE value.
As part of this change, rename the field `eth_mode` in the register cache
to `oen` to better reflect its general purpose and decouple the naming
from a specific register.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 29 +++++++++++++++----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 0021ca1cc988..e24ff882b609 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -146,7 +146,6 @@
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
-#define ETH_MODE (0x3018)
#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
@@ -221,11 +220,13 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
* @pwpr: PWPR register offset
* @sd_ch: SD_CH register offset
* @eth_poc: ETH_POC register offset
+ * @oen: OEN register offset
*/
struct rzg2l_register_offsets {
u16 pwpr;
u16 sd_ch;
u16 eth_poc;
+ u16 oen;
};
/**
@@ -322,7 +323,7 @@ struct rzg2l_pinctrl_pin_settings {
* @ien: IEN registers cache
* @sd_ch: SD_CH registers cache
* @eth_poc: ET_POC registers cache
- * @eth_mode: ETH_MODE register cache
+ * @oen: Output Enable register cache
* @qspi: QSPI registers cache
*/
struct rzg2l_pinctrl_reg_cache {
@@ -335,7 +336,7 @@ struct rzg2l_pinctrl_reg_cache {
u32 *pupd[2];
u8 sd_ch[2];
u8 eth_poc[2];
- u8 eth_mode;
+ u8 oen;
u8 qspi;
};
@@ -1068,11 +1069,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
if (bit < 0)
return 0;
- return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
+ return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
}
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
{
+ u16 oen_offset = pctrl->data->hwcfg->regs.oen;
unsigned long flags;
int bit;
u8 val;
@@ -1082,12 +1084,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
return bit;
spin_lock_irqsave(&pctrl->lock, flags);
- val = readb(pctrl->base + ETH_MODE);
+ val = readb(pctrl->base + oen_offset);
if (oen)
val &= ~BIT(bit);
else
val |= BIT(bit);
- writeb(val, pctrl->base + ETH_MODE);
+ writeb(val, pctrl->base + oen_offset);
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@@ -1121,11 +1123,12 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
if (bit < 0)
return 0;
- return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
+ return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
}
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
{
+ u16 oen_offset = pctrl->data->hwcfg->regs.oen;
unsigned long flags;
int bit;
u8 val;
@@ -1135,12 +1138,12 @@ static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
return bit;
spin_lock_irqsave(&pctrl->lock, flags);
- val = readb(pctrl->base + ETH_MODE);
+ val = readb(pctrl->base + oen_offset);
if (oen)
val &= ~BIT(bit);
else
val |= BIT(bit);
- writeb(val, pctrl->base + ETH_MODE);
+ writeb(val, pctrl->base + oen_offset);
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@@ -3157,7 +3160,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
}
cache->qspi = readb(pctrl->base + QSPI);
- cache->eth_mode = readb(pctrl->base + ETH_MODE);
+ if (pctrl->data->hwcfg->regs.oen)
+ cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
if (!atomic_read(&pctrl->wakeup_path))
clk_disable_unprepare(pctrl->clk);
@@ -3182,7 +3186,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
}
writeb(cache->qspi, pctrl->base + QSPI);
- writeb(cache->eth_mode, pctrl->base + ETH_MODE);
+ if (pctrl->data->hwcfg->regs.oen)
+ writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
for (u8 i = 0; i < 2; i++) {
if (regs->sd_ch)
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
@@ -3234,6 +3239,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
.pwpr = 0x3014,
.sd_ch = 0x3000,
.eth_poc = 0x300c,
+ .oen = 0x3018,
},
.iolh_groupa_ua = {
/* 3v3 power source */
@@ -3249,6 +3255,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
.pwpr = 0x3000,
.sd_ch = 0x3004,
.eth_poc = 0x3010,
+ .oen = 0x3018,
},
.iolh_groupa_ua = {
/* 1v8 power source */
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 05/22] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (3 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 04/22] pinctrl: renesas: rzg2l: Parameterize OEN register offset John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 06/22] pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E John Madieu
` (18 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit a3455a0c24834eaa20f032b214d53b1607d60073 ]
Refactor the RZG2L pinctrl driver to support reuse of the common
rzg2l_read_oen() and rzg2l_write_oen() helpers across SoCs with
different output-enable (OEN) bit mappings.
Introduce a new `pin_to_oen_bit` callback in `struct rzg2l_pinctrl_data`
to allow SoCs to provide custom logic for mapping a pin to its OEN bit.
Update the generic OEN read/write paths to use this callback when present.
With this change, SoCs like RZ/G3S can reuse the common OEN handling
code by simply supplying their own `pin_to_oen_bit` implementation.
The previously duplicated `rzg3s_oen_read()` and `rzg3s_oen_write()`
functions are now removed.
This improves maintainability and prepares the driver for supporting
future SoCs with minimal duplication.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 54 +++++++------------------
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index e24ff882b609..dda610c74120 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -296,6 +296,7 @@ struct rzg2l_pinctrl_data {
#endif
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
+ int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
int (*hw_to_bias_param)(unsigned int val);
@@ -1065,7 +1066,10 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
int bit;
- bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
+ if (!pctrl->data->pin_to_oen_bit)
+ return 0;
+
+ bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
if (bit < 0)
return 0;
@@ -1079,9 +1083,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
int bit;
u8 val;
- bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
+ if (!pctrl->data->pin_to_oen_bit)
+ return -EINVAL;
+
+ bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
if (bit < 0)
- return bit;
+ return -EINVAL;
spin_lock_irqsave(&pctrl->lock, flags);
val = readb(pctrl->base + oen_offset);
@@ -1115,40 +1122,6 @@ static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
return bit;
}
-static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
-{
- int bit;
-
- bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
- if (bit < 0)
- return 0;
-
- return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
-}
-
-static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
-{
- u16 oen_offset = pctrl->data->hwcfg->regs.oen;
- unsigned long flags;
- int bit;
- u8 val;
-
- bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
- if (bit < 0)
- return bit;
-
- spin_lock_irqsave(&pctrl->lock, flags);
- val = readb(pctrl->base + oen_offset);
- if (oen)
- val &= ~BIT(bit);
- else
- val |= BIT(bit);
- writeb(val, pctrl->base + oen_offset);
- spin_unlock_irqrestore(&pctrl->lock, flags);
-
- return 0;
-}
-
static int rzg2l_hw_to_bias_param(unsigned int bias)
{
switch (bias) {
@@ -3305,6 +3278,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
#endif
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
.oen_read = &rzg2l_read_oen,
.oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
@@ -3322,6 +3296,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.hwcfg = &rzg2l_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
.oen_read = &rzg2l_read_oen,
.oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
@@ -3338,8 +3313,9 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.hwcfg = &rzg3s_hwcfg,
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
- .oen_read = &rzg3s_oen_read,
- .oen_write = &rzg3s_oen_write,
+ .pin_to_oen_bit = &rzg3s_pin_to_oen_bit,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 06/22] pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (4 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 05/22] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 07/22] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N} John Madieu
` (17 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit dd0d40d8f4ac8c2cb5967fdb2e1efa70cfc0c9ee ]
The RZ/G3E pin controller does not advertise PIN_CFG_OEN capability, so
there is no valid mapping for output-enable bits on this SoC. Remove the
oen_read and oen_write callbacks from the RZ/G3E driver data to defer
OEN support until PIN_CFG_OEN support is added.
This is a preparatory change for future unification of OEN handling across
the driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index dda610c74120..bce510112e8d 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3337,8 +3337,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
#endif
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
- .oen_read = &rzv2h_oen_read,
- .oen_write = &rzv2h_oen_write,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 07/22] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (5 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 06/22] pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 08/22] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC John Madieu
` (16 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit cd39805be85b8ff45b0ad2715d8de48dbe404cee ]
Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing
rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a
pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit
positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR
locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded
PFC_OEN define and obsolete per-SoC OEN helpers.
Also drop redundant checks for the OEN offset in the suspend/resume paths,
as all supported SoCs now provide a valid offset through the `regs.oen`
field.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 68 ++++++++-----------------
1 file changed, 22 insertions(+), 46 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index bce510112e8d..9c7eeab5b4a4 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -146,7 +146,6 @@
#define SD_CH(off, ch) ((off) + (ch) * 4)
#define ETH_POC(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
-#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
#define PVDD_2500 2 /* I/O domain voltage 2.5V */
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -255,6 +254,7 @@ enum rzg2l_iolh_index {
* @iolh_groupb_oi: IOLH group B output impedance specific values
* @tint_start_index: the start index for the TINT interrupts
* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
+ * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR
* @func_base: base number for port function (see register PFC)
* @oen_max_pin: the maximum pin number supporting output enable
* @oen_max_port: the maximum port number supporting output enable
@@ -267,6 +267,7 @@ struct rzg2l_hwcfg {
u16 iolh_groupb_oi[4];
u16 tint_start_index;
bool drive_strength_ua;
+ bool oen_pwpr_lock;
u8 func_base;
u8 oen_max_pin;
u8 oen_max_port;
@@ -1078,10 +1079,11 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
u16 oen_offset = pctrl->data->hwcfg->regs.oen;
unsigned long flags;
+ u8 val, pwpr;
int bit;
- u8 val;
if (!pctrl->data->pin_to_oen_bit)
return -EINVAL;
@@ -1096,7 +1098,13 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
val &= ~BIT(bit);
else
val |= BIT(bit);
+ if (pctrl->data->hwcfg->oen_pwpr_lock) {
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ }
writeb(val, pctrl->base + oen_offset);
+ if (pctrl->data->hwcfg->oen_pwpr_lock)
+ writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
@@ -1187,7 +1195,7 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
return -EINVAL;
}
-static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
"XSPI0_RESET0N", "XSPI0_CS0N",
@@ -1201,41 +1209,7 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
}
/* Should not happen. */
- return 0;
-}
-
-static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
-{
- u8 bit;
-
- bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
-
- return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
-}
-
-static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
-{
- const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
- const struct rzg2l_register_offsets *regs = &hwcfg->regs;
- unsigned long flags;
- u8 val, bit;
- u8 pwpr;
-
- bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
- spin_lock_irqsave(&pctrl->lock, flags);
- val = readb(pctrl->base + PFC_OEN);
- if (oen)
- val &= ~BIT(bit);
- else
- val |= BIT(bit);
-
- pwpr = readb(pctrl->base + regs->pwpr);
- writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
- writeb(val, pctrl->base + PFC_OEN);
- writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
- spin_unlock_irqrestore(&pctrl->lock, flags);
-
- return 0;
+ return -EINVAL;
}
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
@@ -3133,8 +3107,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
}
cache->qspi = readb(pctrl->base + QSPI);
- if (pctrl->data->hwcfg->regs.oen)
- cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
+ cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
if (!atomic_read(&pctrl->wakeup_path))
clk_disable_unprepare(pctrl->clk);
@@ -3159,8 +3132,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
}
writeb(cache->qspi, pctrl->base + QSPI);
- if (pctrl->data->hwcfg->regs.oen)
- writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
+ writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
for (u8 i = 0; i < 2; i++) {
if (regs->sd_ch)
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
@@ -3260,8 +3232,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
static const struct rzg2l_hwcfg rzv2h_hwcfg = {
.regs = {
.pwpr = 0x3c04,
+ .oen = 0x3c40,
},
.tint_start_index = 17,
+ .oen_pwpr_lock = true,
};
static struct rzg2l_pinctrl_data r9a07g043_data = {
@@ -3358,8 +3332,9 @@ static struct rzg2l_pinctrl_data r9a09g056_data = {
#endif
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
- .oen_read = &rzv2h_oen_read,
- .oen_write = &rzv2h_oen_write,
+ .pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
@@ -3382,8 +3357,9 @@ static struct rzg2l_pinctrl_data r9a09g057_data = {
#endif
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
- .oen_read = &rzv2h_oen_read,
- .oen_write = &rzv2h_oen_write,
+ .pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 08/22] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (6 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 07/22] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N} John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 09/22] pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks John Madieu
` (15 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 54ac76e13ace31cf732bf5261811ef5af67022b7 ]
Add support for configuring the PFC_OEN register on the RZ/G3E SoC to
enable output-enable control for specific pins. On this SoC, certain
pins such as TXC_TXCLK need to support switching between input and
output modes depending on the PHY interface mode (e.g., MII vs RGMII).
This functionality maps to the 'output-enable' property in the device
tree and requires explicit control via the PFC_OEN register.
This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1,
PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable
support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these
pin names to their respective OEN bit positions, and the corresponding
callbacks are wired into the RZ/G3E SoC configuration using the generic
rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO
configuration for the PB, PE, and PL ports is updated to use the variable
port pack macro, enabling per-pin configuration necessary for OEN handling.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 61 +++++++++++++++++++++----
1 file changed, 52 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 9c7eeab5b4a4..0968069aab5a 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -397,6 +397,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
@@ -405,6 +413,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
@@ -424,6 +440,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = {
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS),
+ RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS),
};
static const u64 r9a09g057_variable_pin_cfg[] = {
@@ -1195,23 +1219,39 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
return -EINVAL;
}
-static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin,
+ const char * const pin_names[], unsigned int count)
{
- static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
- "XSPI0_RESET0N", "XSPI0_CS0N",
- "XSPI0_CKN", "XSPI0_CKP" };
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
unsigned int i;
- for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
+ for (i = 0; i < count; i++) {
if (!strcmp(pin_desc->name, pin_names[i]))
return i;
}
- /* Should not happen. */
return -EINVAL;
}
+static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+{
+ static const char * const pin_names[] = {
+ "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N",
+ "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP"
+ };
+
+ return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));
+}
+
+static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+{
+ static const char * const pin_names[] = {
+ "PB1", "PE1", "PL4", "PL1", "PL2", "PL0"
+ };
+
+ return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));
+}
+
static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int _pin,
unsigned long *config)
@@ -2001,17 +2041,17 @@ static const u64 r9a09g047_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
0x0,
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
- RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */
RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
- RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */
RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
0x0,
RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
- RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
+ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */
RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
0x0,
0x0,
@@ -3311,6 +3351,9 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
#endif
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
+ .pin_to_oen_bit = &rzg3e_pin_to_oen_bit,
+ .oen_read = &rzg2l_read_oen,
+ .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 09/22] pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (7 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 08/22] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 10/22] pinctrl: renesas: rzg2l: Fix OEN resume John Madieu
` (14 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 560c633d378a0cf34afcd66c99321d6306a7e937 ]
Remove oen_read and oen_write callbacks from rzg2l_pinctrl_data as
all SoCs now use the same rzg2l_read_oen() and rzg2l_write_oen()
functions directly.
Change rzg2l_read_oen() return type to int for proper error reporting
and update callers to handle errors consistently.
This simplifies the code by removing redundant callbacks and ensures
uniform OEN handling across all supported SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806195555.1372317-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
(cherry picked from commit 560c633d378a0cf34afcd66c99321d6306a7e937)
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 35 +++++++------------------
1 file changed, 9 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 0968069aab5a..2a87d0352fc1 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -298,8 +298,6 @@ struct rzg2l_pinctrl_data {
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
- u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
- int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
int (*hw_to_bias_param)(unsigned int val);
int (*bias_param_to_hw)(enum pin_config_param param);
};
@@ -1087,16 +1085,16 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
return -EINVAL;
}
-static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
+static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
{
int bit;
if (!pctrl->data->pin_to_oen_bit)
- return 0;
+ return -EOPNOTSUPP;
bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
if (bit < 0)
- return 0;
+ return -EINVAL;
return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
}
@@ -1110,7 +1108,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
int bit;
if (!pctrl->data->pin_to_oen_bit)
- return -EINVAL;
+ return -EOPNOTSUPP;
bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);
if (bit < 0)
@@ -1293,11 +1291,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
if (!(cfg & PIN_CFG_OEN))
return -EINVAL;
- if (!pctrl->data->oen_read)
- return -EOPNOTSUPP;
- arg = pctrl->data->oen_read(pctrl, _pin);
- if (!arg)
- return -EINVAL;
+ ret = rzg2l_read_oen(pctrl, _pin);
+ if (ret < 0)
+ return ret;
+ arg = ret;
break;
case PIN_CONFIG_POWER_SOURCE:
@@ -1456,9 +1453,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
if (!(cfg & PIN_CFG_OEN))
return -EINVAL;
- if (!pctrl->data->oen_write)
- return -EOPNOTSUPP;
- ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
+ ret = rzg2l_write_oen(pctrl, _pin, !!arg);
if (ret)
return ret;
break;
@@ -3293,8 +3288,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3311,8 +3304,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3328,8 +3319,6 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzg2l_pmc_writeb,
.pin_to_oen_bit = &rzg3s_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzg2l_hw_to_bias_param,
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
};
@@ -3352,8 +3341,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
.pin_to_oen_bit = &rzg3e_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
@@ -3376,8 +3363,6 @@ static struct rzg2l_pinctrl_data r9a09g056_data = {
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
@@ -3401,8 +3386,6 @@ static struct rzg2l_pinctrl_data r9a09g057_data = {
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
.pmc_writeb = &rzv2h_pmc_writeb,
.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,
- .oen_read = &rzg2l_read_oen,
- .oen_write = &rzg2l_write_oen,
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 10/22] pinctrl: renesas: rzg2l: Fix OEN resume
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (8 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 09/22] pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 11/22] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
` (13 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 30247fc3254a4502465ab809d49e2167ace5a6f2 ]
Writing to the PFC_OEN register is controlled by the write protect
register (PWPR). Currently the OEN register write in resume() is done
without enabling write access in PWPR leading to incorrect operation.
Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[geert: Move spin_*lock*() calls inside if-statements]
Link: https://lore.kernel.org/20250817143024.165471-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2a87d0352fc1..1ea2dc1608b3 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3158,6 +3158,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+ unsigned long flags;
+ u8 pwpr;
int ret;
if (!atomic_read(&pctrl->wakeup_path)) {
@@ -3167,7 +3169,16 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
}
writeb(cache->qspi, pctrl->base + QSPI);
+ if (pctrl->data->hwcfg->oen_pwpr_lock) {
+ spin_lock_irqsave(&pctrl->lock, flags);
+ pwpr = readb(pctrl->base + regs->pwpr);
+ writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ }
writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
+ if (pctrl->data->hwcfg->oen_pwpr_lock) {
+ writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
+ }
for (u8 i = 0; i < 2; i++) {
if (regs->sd_ch)
writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 11/22] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (9 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 10/22] pinctrl: renesas: rzg2l: Fix OEN resume John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 12/22] dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETH John Madieu
` (12 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
[ Upstream commit e6e54229f328c30a1b4ecba1253f9d314dd42e33 ]
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
clocks needed by these two GBETH IPs.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702005706.1200059-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[john.madieu:
- Updated rzv2h-cpg.h header file to define necesaeey macros. That is,
CPG_SSEL0, CSDIV0_DIVCTL0/1, SSEL0_SELCTL2/3, and SSEL1_SELCTL0/1]
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 64 +++++++++++++++++++++++++++++
drivers/clk/renesas/rzv2h-cpg.h | 7 ++++
2 files changed, 71 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 21699999cedd..281d19782409 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -29,6 +29,7 @@ enum clk_ids {
CLK_PLLDTY,
CLK_PLLCA55,
CLK_PLLVDO,
+ CLK_PLLETH,
/* Internal Core Clocks */
CLK_PLLCM33_DIV3,
@@ -46,6 +47,15 @@ enum clk_ids {
CLK_PLLDTY_ACPU,
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
+ CLK_PLLDTY_DIV8,
+ CLK_PLLETH_DIV_250_FIX,
+ CLK_PLLETH_DIV_125_FIX,
+ CLK_CSDIV_PLLETH_GBE0,
+ CLK_CSDIV_PLLETH_GBE1,
+ CLK_SMUX2_GBE0_TXCLK,
+ CLK_SMUX2_GBE0_RXCLK,
+ CLK_SMUX2_GBE1_TXCLK,
+ CLK_SMUX2_GBE1_RXCLK,
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
CLK_PLLVDO_GPU,
@@ -85,7 +95,18 @@ static const struct clk_div_table dtable_2_64[] = {
{0, 0},
};
+static const struct clk_div_table dtable_2_100[] = {
+ {0, 2},
+ {1, 10},
+ {2, 100},
+ {0, 0},
+};
+
/* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
@@ -100,6 +121,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+ DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
/* Internal Core Clocks */
@@ -122,6 +144,18 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+ DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+
+ DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+ DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+ DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,
+ CSDIV0_DIVCTL0, dtable_2_100),
+ DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,
+ CSDIV0_DIVCTL1, dtable_2_100),
+ DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+ DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+ DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+ DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
@@ -139,6 +173,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CDDIV1_DIVCTL3, dtable_1_8),
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
+ DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
+ CLK_PLLETH_DIV_125_FIX, 1, 1),
+ DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
+ CLK_PLLETH_DIV_125_FIX, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -214,6 +252,30 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
+ DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+ BUS_MSTOP(8, BIT(5)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+ BUS_MSTOP(8, BIT(5)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+ BUS_MSTOP(8, BIT(5)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+ BUS_MSTOP(8, BIT(5)), 1),
+ DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+ BUS_MSTOP(8, BIT(5))),
+ DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+ BUS_MSTOP(8, BIT(6)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+ BUS_MSTOP(8, BIT(6)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+ BUS_MSTOP(8, BIT(6)), 1),
+ DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+ BUS_MSTOP(8, BIT(6)), 1),
+ DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+ BUS_MSTOP(8, BIT(6))),
+ DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+ BUS_MSTOP(8, BIT(6))),
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
BUS_MSTOP(9, BIT(4))),
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -255,6 +317,8 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
+ DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 543e44904bba..34423bd4d3e1 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -111,6 +111,7 @@ struct fixed_mod_conf {
.mon_bit = (_bit), \
})
+#define CPG_SSEL0 (0x300)
#define CPG_SSEL1 (0x304)
#define CPG_CDDIV0 (0x400)
#define CPG_CDDIV1 (0x404)
@@ -131,8 +132,14 @@ struct fixed_mod_conf {
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
+#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
+#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
+#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
+#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
+#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1)
+#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 12/22] dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETH
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (10 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 11/22] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 13/22] dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC John Madieu
` (11 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 8fff7ae84d1880b7d435f3bb71518eb24bf84846 ]
GBETH IP on the Renesas RZ/V2H(P) SoC is integrated with Synopsys
DesignWare MAC (version 5.20). Document the device tree bindings for
the GBETH glue layer.
Generic compatible string 'renesas,rzv2h-gbeth' is added since this
module is identical on both the RZ/V2H(P) and RZ/G3E SoCs.
The Rx/Tx clocks supplied for GBETH on the RZ/V2H(P) SoC is depicted
below:
Rx / Tx
-------+------------- on / off -------
|
| Rx-180 / Tx-180
+---- not ---- on / off -------
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250417084015.74154-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../bindings/net/renesas,r9a09g057-gbeth.yaml | 201 ++++++++++++++++++
.../devicetree/bindings/net/snps,dwmac.yaml | 1 +
2 files changed, 202 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
diff --git a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
new file mode 100644
index 000000000000..02a6793c26f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g057-gbeth
+ - renesas,rzv2h-gbeth
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a09g057-gbeth # RZ/V2H(P)
+ - const: renesas,rzv2h-gbeth
+ - const: snps,dwmac-5.20
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: CSR clock
+ - description: AXI system clock
+ - description: PTP clock
+ - description: TX clock
+ - description: RX clock
+ - description: TX clock phase-shifted by 180 degrees
+ - description: RX clock phase-shifted by 180 degrees
+
+ clock-names:
+ items:
+ - const: stmmaceth
+ - const: pclk
+ - const: ptp_ref
+ - const: tx
+ - const: rx
+ - const: tx-180
+ - const: rx-180
+
+ interrupts:
+ minItems: 11
+
+ interrupt-names:
+ items:
+ - const: macirq
+ - const: eth_wake_irq
+ - const: eth_lpi
+ - const: rx-queue-0
+ - const: rx-queue-1
+ - const: rx-queue-2
+ - const: rx-queue-3
+ - const: tx-queue-0
+ - const: tx-queue-1
+ - const: tx-queue-2
+ - const: tx-queue-3
+
+ resets:
+ items:
+ - description: AXI power-on system reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - resets
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ethernet@15c30000 {
+ compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20";
+ reg = <0x15c30000 0x10000>;
+ clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
+ <&ptp_clock>, <&cpg CPG_MOD 0xb8>,
+ <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>,
+ <&cpg CPG_MOD 0xbb>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "rx", "tx-180", "rx-180";
+ resets = <&cpg 0xb0>;
+ interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "tx-queue-0", "tx-queue-1",
+ "tx-queue-2", "tx-queue-3";
+ phy-mode = "rgmii-id";
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ phy-handle = <&phy0>;
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 4e2ba1bf788c..f1cc9271e0c4 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -72,6 +72,7 @@ properties:
- qcom,sm8150-ethqos
- renesas,r9a06g032-gmac
- renesas,rzn1-gmac
+ - renesas,rzv2h-gbeth
- rockchip,px30-gmac
- rockchip,rk3128-gmac
- rockchip,rk3228-gmac
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 13/22] dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (11 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 12/22] dt-bindings: net: Document support for Renesas RZ/V2H(P) GBETH John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 14/22] dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml John Madieu
` (10 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
[ Upstream commit 31b928210df1097eaa5e8cb51e2ff79989ebe57e ]
Document support for the GBETH IP found on the Renesas RZ/G3E (R9A09G047) SoC.
The GBETH block on RZ/G3E is equivalent in functionality to the GBETH found on
RZ/V2H(P) (R9A09G057).
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250611061204.15393-1-john.madieu.xa@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
index 02a6793c26f5..91f637b048ab 100644
--- a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
@@ -14,6 +14,7 @@ select:
compatible:
contains:
enum:
+ - renesas,r9a09g047-gbeth
- renesas,r9a09g057-gbeth
- renesas,rzv2h-gbeth
required:
@@ -23,6 +24,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,r9a09g047-gbeth # RZ/G3E
- renesas,r9a09g057-gbeth # RZ/V2H(P)
- const: renesas,rzv2h-gbeth
- const: snps,dwmac-5.20
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 14/22] dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (12 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 13/22] dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:37 ` [PATCH 6.12.y-cip 15/22] net: phy: Add helper for mapping RGMII link speed to clock rate John Madieu
` (9 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Geert Uytterhoeven <geert+renesas@glider.be>
[ Upstream commit d53320aeef18ece4999c0cf07cb802d1dd990885 ]
The DT bindings file "renesas,r9a09g057-gbeth.yaml" applies to a whole
family of SoCs, and uses "renesas,rzv2h-gbeth" as a fallback compatible
value. Hence rename it to the more generic "renesas,rzv2h-gbeth.yaml".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/721f6e0e09777e0842ecaca4578bc50c953d2428.1750838954.git.geert+renesas@glider.be
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../{renesas,r9a09g057-gbeth.yaml => renesas,rzv2h-gbeth.yaml} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/net/{renesas,r9a09g057-gbeth.yaml => renesas,rzv2h-gbeth.yaml} (98%)
diff --git a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
similarity index 98%
rename from Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
rename to Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
index 91f637b048ab..ee8fbb6c7994 100644
--- a/Documentation/devicetree/bindings/net/renesas,r9a09g057-gbeth.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/net/renesas,r9a09g057-gbeth.yaml#
+$id: http://devicetree.org/schemas/net/renesas,rzv2h-gbeth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GBETH glue layer for Renesas RZ/V2H(P) (and similar SoCs)
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 15/22] net: phy: Add helper for mapping RGMII link speed to clock rate
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (13 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 14/22] dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml John Madieu
@ 2025-11-03 11:37 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 16/22] net: stmmac: provide set_clk_tx_rate() hook John Madieu
` (8 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:37 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
[ Upstream commit 386aa60abdb600a4e5ad818e6dba171685942e54 ]
The RGMII interface supports three data rates: 10/100 Mbps
and 1 Gbps. These speeds correspond to clock frequencies
of 2.5/25 MHz and 125 MHz, respectively.
Many Ethernet drivers, including glues in stmmac, follow
a similar pattern of converting RGMII speed to clock frequency.
To simplify code, define the helper rgmii_clock(speed)
to convert connection speed to clock frequency.
Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Link: https://patch.msgid.link/20241205-upstream_s32cc_gmac-v8-4-ec1d180df815@oss.nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
include/linux/phy.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index dfc7b97f9648..89aa0df5e5cf 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -298,6 +298,29 @@ static inline const char *phy_modes(phy_interface_t interface)
}
}
+/**
+ * rgmii_clock - map link speed to the clock rate
+ * @speed: link speed value
+ *
+ * Description: maps RGMII supported link speeds
+ * into the clock rates.
+ *
+ * Returns: clock rate or negative errno
+ */
+static inline long rgmii_clock(int speed)
+{
+ switch (speed) {
+ case SPEED_10:
+ return 2500000;
+ case SPEED_100:
+ return 25000000;
+ case SPEED_1000:
+ return 125000000;
+ default:
+ return -EINVAL;
+ }
+}
+
#define PHY_INIT_TIMEOUT 100000
#define PHY_FORCE_TIMEOUT 10
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 16/22] net: stmmac: provide set_clk_tx_rate() hook
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (14 preceding siblings ...)
2025-11-03 11:37 ` [PATCH 6.12.y-cip 15/22] net: phy: Add helper for mapping RGMII link speed to clock rate John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 17/22] net: stmmac: provide generic implementation for set_clk_tx_rate method John Madieu
` (7 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
[ Upstream commit dea5c8ec20be7603e4a56b9d6571321f330626c1 ]
Several stmmac sub-drivers which support RGMII follow the same pattern.
They calculate the transmit clock rate, and then call clk_set_rate().
Analysis of several implementation documents suggests that the platform
is responsible for providing the transmit clock to the DWMAC core's
clk_tx_i. The expected rates are:
10Mbps 100Mbps 1Gbps
MII 2.5MHz 25MHz
RMII 2.5MHz 25MHz
GMII 125MHz
RGMI 2.5MHz 25MHz 125MHz
It seems some platforms require this clock to be manually configured,
but there are outputs from the MAC core that indicate the speed, so a
platform may use these to automatically configure the clock. Thus, we
can't just provide one solution to configure this clock rate.
Moreover, the clock may need to be derived from one of several sources
depending on the interface mode.
Provide a platform hook that is passed the transmit clock, interface
mode and speed.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1tna0F-0052sS-Lr@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 +++++++++++
include/linux/stmmac.h | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 40d56ff66b6a..2c2ba1dba80d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1023,6 +1023,7 @@ static void stmmac_mac_link_up(struct phylink_config *config,
{
struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
u32 old_ctrl, ctrl;
+ int ret;
if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
priv->plat->serdes_powerup)
@@ -1115,6 +1116,16 @@ static void stmmac_mac_link_up(struct phylink_config *config,
if (ctrl != old_ctrl)
writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
+ if (priv->plat->set_clk_tx_rate) {
+ ret = priv->plat->set_clk_tx_rate(priv->plat->bsp_priv,
+ priv->plat->clk_tx_i,
+ interface, speed);
+ if (ret < 0)
+ netdev_err(priv->dev,
+ "failed to configure transmit clock for %dMbps: %pe\n",
+ speed, ERR_PTR(ret));
+ }
+
stmmac_mac_set(priv, priv->ioaddr, true);
if (phy && priv->dma_cap.eee) {
priv->eee_active =
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index d79ff252cfdc..dadf861138e3 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -76,6 +76,7 @@
| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
+struct clk;
struct stmmac_priv;
/* Platfrom data for platform device structure's platform_data field */
@@ -229,6 +230,8 @@ struct plat_stmmacenet_data {
u8 tx_sched_algorithm;
struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
+ int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
+ phy_interface_t interface, int speed);
void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
int (*serdes_powerup)(struct net_device *ndev, void *priv);
@@ -250,6 +253,7 @@ struct plat_stmmacenet_data {
struct clk *stmmac_clk;
struct clk *pclk;
struct clk *clk_ptp_ref;
+ struct clk *clk_tx_i; /* clk_tx_i to MAC core */
unsigned int clk_ptp_rate;
unsigned int clk_ref_rate;
unsigned int mult_fact_100ns;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 17/22] net: stmmac: provide generic implementation for set_clk_tx_rate method
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (15 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 16/22] net: stmmac: provide set_clk_tx_rate() hook John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 18/22] net: stmmac: provide stmmac_pltfr_find_clk() John Madieu
` (6 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
[ Upstream commit 12bce6d5404ea30180536322c1ad31bc45a988d2 ]
Provide a generic implementation for the set_clk_tx_rate method
introduced by the previous patch, which is capable of configuring the
MAC transmit clock for 10M, 100M and 1000M speeds for at least MII,
GMII, RGMII and RMII interface modes.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1tna0K-0052sY-QF@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 32 +++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index ea135203ff2e..7a976aab322f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -421,6 +421,8 @@ int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
void stmmac_fpe_apply(struct stmmac_priv *priv);
+int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
+ phy_interface_t interface, int speed);
static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 2c2ba1dba80d..557d442c3713 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -179,6 +179,38 @@ int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
}
EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
+/**
+ * stmmac_set_clk_tx_rate() - set the clock rate for the MAC transmit clock
+ * @bsp_priv: BSP private data structure (unused)
+ * @clk_tx_i: the transmit clock
+ * @interface: the selected interface mode
+ * @speed: the speed that the MAC will be operating at
+ *
+ * Set the transmit clock rate for the MAC, normally 2.5MHz for 10Mbps,
+ * 25MHz for 100Mbps and 125MHz for 1Gbps. This is suitable for at least
+ * MII, GMII, RGMII and RMII interface modes. Platforms can hook this into
+ * the plat_data->set_clk_tx_rate method directly, call it via their own
+ * implementation, or implement their own method should they have more
+ * complex requirements. It is intended to only be used in this method.
+ *
+ * plat_data->clk_tx_i must be filled in.
+ */
+int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
+ phy_interface_t interface, int speed)
+{
+ long rate = rgmii_clock(speed);
+
+ /* Silently ignore unsupported speeds as rgmii_clock() only
+ * supports 10, 100 and 1000Mbps. We do not want to spit
+ * errors for 2500 and higher speeds here.
+ */
+ if (rate < 0)
+ return 0;
+
+ return clk_set_rate(clk_tx_i, rate);
+}
+EXPORT_SYMBOL_GPL(stmmac_set_clk_tx_rate);
+
/**
* stmmac_verify_args - verify the driver parameters.
* Description: it checks the driver parameters and set a default in case of
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 18/22] net: stmmac: provide stmmac_pltfr_find_clk()
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (16 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 17/22] net: stmmac: provide generic implementation for set_clk_tx_rate method John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH John Madieu
` (5 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
[ Upstream commit de64872019492e4a84ee053e635cdf8f63f853d2 ]
Provide a generic way to find a clock in the bulk data.
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1u2QO4-001Rp2-Dy@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
[john.madieu:
- Added clks and num_clks fields in plat_stmmacenet_data]
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 11 +++++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h | 3 +++
include/linux/stmmac.h | 2 ++
3 files changed, 16 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8fd868b671a2..0c7c7c29d6eb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -705,6 +705,17 @@ devm_stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
#endif /* CONFIG_OF */
EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt);
+struct clk *stmmac_pltfr_find_clk(struct plat_stmmacenet_data *plat_dat,
+ const char *name)
+{
+ for (int i = 0; i < plat_dat->num_clks; i++)
+ if (strcmp(plat_dat->clks[i].id, name) == 0)
+ return plat_dat->clks[i].clk;
+
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk);
+
int stmmac_get_platform_resources(struct platform_device *pdev,
struct stmmac_resources *stmmac_res)
{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
index 72dc1a32e46d..6e6561e29d6e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
@@ -14,6 +14,9 @@
struct plat_stmmacenet_data *
devm_stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac);
+struct clk *stmmac_pltfr_find_clk(struct plat_stmmacenet_data *plat_dat,
+ const char *name);
+
int stmmac_get_platform_resources(struct platform_device *pdev,
struct stmmac_resources *stmmac_res);
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index dadf861138e3..69b246b6ebef 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -256,6 +256,8 @@ struct plat_stmmacenet_data {
struct clk *clk_tx_i; /* clk_tx_i to MAC core */
unsigned int clk_ptp_rate;
unsigned int clk_ref_rate;
+ struct clk_bulk_data *clks;
+ int num_clks;
unsigned int mult_fact_100ns;
s32 ptp_max_adj;
u32 cdc_error_adj;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (17 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 18/22] net: stmmac: provide stmmac_pltfr_find_clk() John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-04 12:45 ` Pavel Machek
2025-11-03 11:38 ` [PATCH 6.12.y-cip 20/22] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
` (4 subsequent siblings)
23 siblings, 1 reply; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
[ Upstream commit 461f6529e5946d98ef91bf115d5ced61d8439a6a ]
Add the DWMAC glue layer for the GBETH IP found in the Renesas RZ/V2H(P)
SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://patch.msgid.link/20250417084015.74154-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
[john.madieu:
- Removed STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP flag as it's not available
in 6.12.y-cip]
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../stmicro/stmmac/dwmac-renesas-gbeth.c | 146 ++++++++++++++++++
3 files changed, 158 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 05cc07b8f48c..fcf5da66fd02 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -131,6 +131,17 @@ config DWMAC_QCOM_ETHQOS
This selects the Qualcomm ETHQOS glue layer support for the
stmmac device driver.
+config DWMAC_RENESAS_GBETH
+ tristate "Renesas RZ/V2H(P) GBETH support"
+ default ARCH_RENESAS
+ depends on OF && (ARCH_RENESAS || COMPILE_TEST)
+ help
+ Support for Gigabit Ethernet Interface (GBETH) on Renesas
+ RZ/V2H(P) SoCs.
+
+ This selects the Renesas RZ/V2H(P) Soc specific glue layer support
+ for the stmmac device driver.
+
config DWMAC_ROCKCHIP
tristate "Rockchip dwmac support"
default ARCH_ROCKCHIP
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index c2f0e91f6bf8..dd53002cbfb0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o
obj-$(CONFIG_DWMAC_MEDIATEK) += dwmac-mediatek.o
obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
+obj-$(CONFIG_DWMAC_RENESAS_GBETH) += dwmac-renesas-gbeth.o
obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
new file mode 100644
index 000000000000..8bd554bf94f9
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dwmac-renesas-gbeth.c - DWMAC Specific Glue layer for Renesas GBETH
+ *
+ * The Rx and Tx clocks are supplied as follows for the GBETH IP.
+ *
+ * Rx / Tx
+ * -------+------------- on / off -------
+ * |
+ * | Rx-180 / Tx-180
+ * +---- not ---- on / off -------
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "stmmac_platform.h"
+
+struct renesas_gbeth {
+ struct plat_stmmacenet_data *plat_dat;
+ struct reset_control *rstc;
+ struct device *dev;
+};
+
+static const char *const renesas_gbeth_clks[] = {
+ "tx", "tx-180", "rx", "rx-180",
+};
+
+static int renesas_gbeth_init(struct platform_device *pdev, void *priv)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct renesas_gbeth *gbeth = priv;
+ int ret;
+
+ plat_dat = gbeth->plat_dat;
+
+ ret = reset_control_deassert(gbeth->rstc);
+ if (ret) {
+ dev_err(gbeth->dev, "Reset deassert failed\n");
+ return ret;
+ }
+
+ ret = clk_bulk_prepare_enable(plat_dat->num_clks,
+ plat_dat->clks);
+ if (ret)
+ reset_control_assert(gbeth->rstc);
+
+ return ret;
+}
+
+static void renesas_gbeth_exit(struct platform_device *pdev, void *priv)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct renesas_gbeth *gbeth = priv;
+ int ret;
+
+ plat_dat = gbeth->plat_dat;
+
+ clk_bulk_disable_unprepare(plat_dat->num_clks, plat_dat->clks);
+
+ ret = reset_control_assert(gbeth->rstc);
+ if (ret)
+ dev_err(gbeth->dev, "Reset assert failed\n");
+}
+
+static int renesas_gbeth_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat_dat;
+ struct stmmac_resources stmmac_res;
+ struct device *dev = &pdev->dev;
+ struct renesas_gbeth *gbeth;
+ unsigned int i;
+ int err;
+
+ err = stmmac_get_platform_resources(pdev, &stmmac_res);
+ if (err)
+ return dev_err_probe(dev, err,
+ "failed to get resources\n");
+
+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
+ if (IS_ERR(plat_dat))
+ return dev_err_probe(dev, PTR_ERR(plat_dat),
+ "dt configuration failed\n");
+
+ gbeth = devm_kzalloc(dev, sizeof(*gbeth), GFP_KERNEL);
+ if (!gbeth)
+ return -ENOMEM;
+
+ plat_dat->num_clks = ARRAY_SIZE(renesas_gbeth_clks);
+ plat_dat->clks = devm_kcalloc(dev, plat_dat->num_clks,
+ sizeof(*plat_dat->clks), GFP_KERNEL);
+ if (!plat_dat->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < plat_dat->num_clks; i++)
+ plat_dat->clks[i].id = renesas_gbeth_clks[i];
+
+ err = devm_clk_bulk_get(dev, plat_dat->num_clks, plat_dat->clks);
+ if (err < 0)
+ return err;
+
+ plat_dat->clk_tx_i = stmmac_pltfr_find_clk(plat_dat, "tx");
+ if (!plat_dat->clk_tx_i)
+ return dev_err_probe(dev, -EINVAL,
+ "error finding tx clock\n");
+
+ gbeth->rstc = devm_reset_control_get_exclusive(dev, NULL);
+ if (IS_ERR(gbeth->rstc))
+ return PTR_ERR(gbeth->rstc);
+
+ gbeth->dev = dev;
+ gbeth->plat_dat = plat_dat;
+ plat_dat->bsp_priv = gbeth;
+ plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
+ plat_dat->init = renesas_gbeth_init;
+ plat_dat->exit = renesas_gbeth_exit;
+
+ plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY |
+ STMMAC_FLAG_SPH_DISABLE;
+
+ return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
+}
+
+static const struct of_device_id renesas_gbeth_match[] = {
+ { .compatible = "renesas,rzv2h-gbeth", },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, renesas_gbeth_match);
+
+static struct platform_driver renesas_gbeth_driver = {
+ .probe = renesas_gbeth_probe,
+ .driver = {
+ .name = "renesas-gbeth",
+ .of_match_table = renesas_gbeth_match,
+ },
+};
+module_platform_driver(renesas_gbeth_driver);
+
+MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas GBETH DWMAC Specific Glue layer");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH
2025-11-03 11:38 ` [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH John Madieu
@ 2025-11-04 12:45 ` Pavel Machek
2025-11-04 18:25 ` John Madieu
0 siblings, 1 reply; 33+ messages in thread
From: Pavel Machek @ 2025-11-04 12:45 UTC (permalink / raw)
To: John Madieu; +Cc: cip-dev, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 928 bytes --]
Hi!
> [ Upstream commit 461f6529e5946d98ef91bf115d5ced61d8439a6a ]
>
> Add the DWMAC glue layer for the GBETH IP found in the Renesas RZ/V2H(P)
> SoC.
> @@ -131,6 +131,17 @@ config DWMAC_QCOM_ETHQOS
> This selects the Qualcomm ETHQOS glue layer support for the
> stmmac device driver.
>
> +config DWMAC_RENESAS_GBETH
> + tristate "Renesas RZ/V2H(P) GBETH support"
> + default ARCH_RENESAS
> + depends on OF && (ARCH_RENESAS || COMPILE_TEST)
> + help
> + Support for Gigabit Ethernet Interface (GBETH) on Renesas
> + RZ/V2H(P) SoCs.
> +
> + This selects the Renesas RZ/V2H(P) Soc specific glue layer support
> + for the stmmac device driver.
> +
I believe "Soc specific" -> "SoC specific" should be done for
consistency.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH
2025-11-04 12:45 ` Pavel Machek
@ 2025-11-04 18:25 ` John Madieu
0 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-04 18:25 UTC (permalink / raw)
To: Pavel Machek; +Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
Hi Pavel,
Thanks for the review.
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Tuesday, November 4, 2025 1:45 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Subject: Re: [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer
> for Renesas GBETH
>
> Hi!
>
> > [ Upstream commit 461f6529e5946d98ef91bf115d5ced61d8439a6a ]
> >
> > Add the DWMAC glue layer for the GBETH IP found in the Renesas
> > RZ/V2H(P) SoC.
>
> > @@ -131,6 +131,17 @@ config DWMAC_QCOM_ETHQOS
> > This selects the Qualcomm ETHQOS glue layer support for the
> > stmmac device driver.
> >
> > +config DWMAC_RENESAS_GBETH
> > + tristate "Renesas RZ/V2H(P) GBETH support"
> > + default ARCH_RENESAS
> > + depends on OF && (ARCH_RENESAS || COMPILE_TEST)
> > + help
> > + Support for Gigabit Ethernet Interface (GBETH) on Renesas
> > + RZ/V2H(P) SoCs.
> > +
> > + This selects the Renesas RZ/V2H(P) Soc specific glue layer
> support
> > + for the stmmac device driver.
> > +
>
> I believe "Soc specific" -> "SoC specific" should be done for
> consistency.
>
Indeed, thanks for pointing it. This will be fixed upstream and then
backported.
> Best regards,
Regards,
John.
> Pavel
> --
> In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
> Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 6.12.y-cip 20/22] arm64: dts: renesas: r9a09g047: Add GBETH nodes
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (18 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 19/22] net: stmmac: Add DWMAC glue layer for Renesas GBETH John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 21/22] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
` (3 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
[ Upstream commit 41ffbb1c42d30a173cc43e931bbaf7bf29e92d1f ]
Add GBETH nodes to RZ/G3E (R9A09G047) SoC DTSI.
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Link: https://lore.kernel.org/20250623080405.355083-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 209 +++++++++++++++++++++
1 file changed, 209 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index a0d4fab4fe05..e4fac7e0d764 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -691,6 +691,208 @@ sdhi2_vqmmc: vqmmc-regulator {
};
};
+ eth0: ethernet@15c30000 {
+ compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
+ "snps,dwmac-5.20";
+ reg = <0 0x15c30000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>,
+ <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>,
+ <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>,
+ <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "rx", "tx-180", "rx-180";
+ interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "tx-queue-0", "tx-queue-1",
+ "tx-queue-2", "tx-queue-3";
+ resets = <&cpg 0xb0>;
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup0>;
+ snps,mtl-tx-config = <&mtl_tx_setup0>;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup0: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+ };
+
+ mtl_tx_setup0: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+ };
+ };
+
+ eth1: ethernet@15c40000 {
+ compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth",
+ "snps,dwmac-5.20";
+ reg = <0 0x15c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>,
+ <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>,
+ <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>,
+ <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref",
+ "tx", "rx", "tx-180", "rx-180";
+ interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "tx-queue-0", "tx-queue-1",
+ "tx-queue-2", "tx-queue-3";
+ resets = <&cpg 0xb1>;
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,txpbl = <32>;
+ snps,rxpbl = <32>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ };
+ };
+ };
+
cru: video@16000000 {
compatible = "renesas,r9a09g047-cru";
reg = <0 0x16000000 0 0x400>;
@@ -761,6 +963,13 @@ csi2cru: endpoint@0 {
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 21/22] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (19 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 20/22] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-03 11:38 ` [PATCH 6.12.y-cip 22/22] arm64: dts: renesas: r9a09g047: Enable Tx coe support John Madieu
` (2 subsequent siblings)
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
[ Upstream commit 0c62020d2a51edba49c73e8469d0fdade8a5cacc ]
Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3E SMARC EVK
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702005706.1200059-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
.../boot/dts/renesas/rzg3e-smarc-som.dtsi | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index f99a09d04ddd..7faa44510d98 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -26,6 +26,8 @@ / {
compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
i2c2 = &i2c2;
mmc0 = &sdhi0;
mmc2 = &sdhi2;
@@ -77,6 +79,24 @@ &audio_extal_clk {
clock-frequency = <48000000>;
};
+ð0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+ð1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&gpu {
status = "okay";
mali-supply = <®_vdd0p8v_others>;
@@ -102,7 +122,98 @@ raa215300: pmic@12 {
};
};
+&mdio0 {
+ phy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <1400>;
+ txc-skew-psec = <1400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+
+&mdio1 {
+ phy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-id0022.1640",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
+ rxc-skew-psec = <1400>;
+ txc-skew-psec = <1400>;
+ rxdv-skew-psec = <0>;
+ txdv-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+
&pinctrl {
+ eth0_pins: eth0 {
+ clk {
+ pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
+ output-enable;
+ };
+
+ ctrl {
+ pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
+ <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
+ <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
+ <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
+ <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
+ <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
+ <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
+ <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
+ <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
+ <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
+ <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
+ <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
+ <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
+ <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
+ };
+ };
+
+ eth1_pins: eth1 {
+ clk {
+ pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
+ output-enable;
+ };
+
+ ctrl {
+
+ pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
+ <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
+ <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
+ <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
+ <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
+ <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
+ <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
+ <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
+ <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
+ <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
+ <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
+ <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
+ <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
+ <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
+ };
+ };
+
i2c2_pins: i2c {
pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PATCH 6.12.y-cip 22/22] arm64: dts: renesas: r9a09g047: Enable Tx coe support
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (20 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 21/22] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
@ 2025-11-03 11:38 ` John Madieu
2025-11-05 9:20 ` [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support Pavel Machek
2025-11-06 19:11 ` Pavel Machek
23 siblings, 0 replies; 33+ messages in thread
From: John Madieu @ 2025-11-03 11:38 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
[ Upstream commit da7326322d31eb60fea27be30ca013d1e9b0a86c ]
The GBETH IPs found on RZ/G3E SoC family are compatible with the stmmac
driver. They have a MAC HW feature register used by this driver to
enable respective features. While the register advertises Tx coe
support, it was not enabled by the driver due to the
'snps,force_thresh_dma_mode' dtsi property.
Switch from 'snps,force_thresh_dma_mode' to 'snps,force_sf_dma_mode' to
enable Tx checksum offload support on both GBETH IPs. While at it, also
switch from 'snps,fixed-burst' to 'snps,mixed-burst' and remove
'snps,no-pbl-x8' for optimal DMA configuration. This improvement
results in a measurable TCP Tx performance gain, increasing throughput
by 20Mbps.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250814153456.268208-1-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764..b55b113d1f11 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -722,9 +722,8 @@ eth0: ethernet@15c30000 {
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
- snps,fixed-burst;
- snps,no-pbl-x8;
- snps,force_thresh_dma_mode;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup0>;
snps,mtl-tx-config = <&mtl_tx_setup0>;
@@ -823,9 +822,8 @@ eth1: ethernet@15c40000 {
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
- snps,fixed-burst;
- snps,no-pbl-x8;
- snps,force_thresh_dma_mode;
+ snps,mixed-burst;
+ snps,force_sf_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (21 preceding siblings ...)
2025-11-03 11:38 ` [PATCH 6.12.y-cip 22/22] arm64: dts: renesas: r9a09g047: Enable Tx coe support John Madieu
@ 2025-11-05 9:20 ` Pavel Machek
2025-11-05 9:30 ` [cip-dev] " Biju Das
2025-11-06 19:11 ` Pavel Machek
23 siblings, 1 reply; 33+ messages in thread
From: Pavel Machek @ 2025-11-05 9:20 UTC (permalink / raw)
To: John Madieu; +Cc: cip-dev, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 661 bytes --]
Hi!
> Add RZ/G3E GBETH support to cip-6.12. While at it, also backport RZ/V2N Pinctrl and
> OEN dependencies.
I agree that most of the issues are best solved in mainline and should
not block merge (provided this passes testing and there are no other
comments).
Please take a look at
"[cip-dev] [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for..."
It may make sense to put that one at end of series, and I can probably
do it while applying, but I'd like confirmation.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread* RE: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-05 9:20 ` [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support Pavel Machek
@ 2025-11-05 9:30 ` Biju Das
2025-11-05 10:48 ` Pavel Machek
0 siblings, 1 reply; 33+ messages in thread
From: Biju Das @ 2025-11-05 9:30 UTC (permalink / raw)
To: pavel@denx.de, John Madieu
Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
Hi Pavel,
> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via
> lists.cip-project.org
> Sent: 05 November 2025 09:21
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
>
> Hi!
>
> > Add RZ/G3E GBETH support to cip-6.12. While at it, also backport
> > RZ/V2N Pinctrl and OEN dependencies.
>
> I agree that most of the issues are best solved in mainline and should not block merge (provided this
> passes testing and there are no other comments).
>
> Please take a look at
>
> "[cip-dev] [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for..."
>
> It may make sense to put that one at end of series, and I can probably do it while applying, but I'd
> like confirmation.
We planned to add RZ/V2N later on 6.1. To cleanly apply RZ/G3E pinctrl patches from mainline, we need
RZ/V2N pinctrl patches which depends on that config option for building it.
So, it makes sense to add Config option before RZ/V2N pinctrl patches, so that at least we can build it.
Cheers,
Biju
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-05 9:30 ` [cip-dev] " Biju Das
@ 2025-11-05 10:48 ` Pavel Machek
2025-11-05 11:40 ` Biju Das
0 siblings, 1 reply; 33+ messages in thread
From: Pavel Machek @ 2025-11-05 10:48 UTC (permalink / raw)
To: biju.das.jz; +Cc: John Madieu, cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 1438 bytes --]
Hi!
> > > Add RZ/G3E GBETH support to cip-6.12. While at it, also backport
> > > RZ/V2N Pinctrl and OEN dependencies.
> >
> > I agree that most of the issues are best solved in mainline and should not block merge (provided this
> > passes testing and there are no other comments).
> >
> > Please take a look at
> >
> > "[cip-dev] [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for..."
> >
> > It may make sense to put that one at end of series, and I can probably do it while applying, but I'd
> > like confirmation.
>
> We planned to add RZ/V2N later on 6.1. To cleanly apply RZ/G3E pinctrl patches from mainline, we need
> RZ/V2N pinctrl patches which depends on that config option for building it.
>
> So, it makes sense to add Config option before RZ/V2N pinctrl patches, so that at least we can build it.
>
What I'm saying is that having kernel with
+config ARCH_R9A09G056
+ bool "ARM64 Platform support for RZ/V2N"
+ default y if ARCH_RENESAS
+ help
+ This enables support for the Renesas RZ/V2N SoC variants.
but no working rz/v2n support seems to be confusing to me, and I don't
believe that's a way things are usually done. Can you correct me or
explain why it is required here?
Thanks and best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* RE: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-05 10:48 ` Pavel Machek
@ 2025-11-05 11:40 ` Biju Das
2025-11-06 11:54 ` Pavel Machek
0 siblings, 1 reply; 33+ messages in thread
From: Biju Das @ 2025-11-05 11:40 UTC (permalink / raw)
To: Pavel Machek
Cc: John Madieu, cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 05 November 2025 10:49
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: John Madieu <john.madieu.xa@bp.renesas.com>; cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
>
> Hi!
>
> > > > Add RZ/G3E GBETH support to cip-6.12. While at it, also backport
> > > > RZ/V2N Pinctrl and OEN dependencies.
> > >
> > > I agree that most of the issues are best solved in mainline and
> > > should not block merge (provided this passes testing and there are no other comments).
> > >
> > > Please take a look at
> > >
> > > "[cip-dev] [PATCH 6.12.y-cip 01/22] soc: renesas: Add config option for..."
> > >
> > > It may make sense to put that one at end of series, and I can
> > > probably do it while applying, but I'd like confirmation.
> >
> > We planned to add RZ/V2N later on 6.1. To cleanly apply RZ/G3E pinctrl
> > patches from mainline, we need RZ/V2N pinctrl patches which depends on that config option for
> building it.
> >
> > So, it makes sense to add Config option before RZ/V2N pinctrl patches, so that at least we can build
> it.
> >
>
> What I'm saying is that having kernel with
>
> +config ARCH_R9A09G056
> + bool "ARM64 Platform support for RZ/V2N"
> + default y if ARCH_RENESAS
> + help
> + This enables support for the Renesas RZ/V2N SoC variants.
>
> but no working rz/v2n support seems to be confusing to me, and I don't believe that's a way things are
> usually done. Can you correct me or explain why it is required here?
It is just added for build coverage for RZ/V2N pinctrl driver. If you think it is wrong
Please move it to last or drop it.
Cheers,
Biju
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [cip-dev] [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-05 11:40 ` Biju Das
@ 2025-11-06 11:54 ` Pavel Machek
0 siblings, 0 replies; 33+ messages in thread
From: Pavel Machek @ 2025-11-06 11:54 UTC (permalink / raw)
To: Biju Das; +Cc: John Madieu, cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 868 bytes --]
Hi!
> > What I'm saying is that having kernel with
> >
> > +config ARCH_R9A09G056
> > + bool "ARM64 Platform support for RZ/V2N"
> > + default y if ARCH_RENESAS
> > + help
> > + This enables support for the Renesas RZ/V2N SoC variants.
> >
> > but no working rz/v2n support seems to be confusing to me, and I don't believe that's a way things are
> > usually done. Can you correct me or explain why it is required here?
>
> It is just added for build coverage for RZ/V2N pinctrl driver. If you think it is wrong
> Please move it to last or drop it.
So this builds and tests okay. I'll apply it with the config option
dropped unless there are other comments.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support
2025-11-03 11:37 [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support John Madieu
` (22 preceding siblings ...)
2025-11-05 9:20 ` [PATCH 6.12.y-cip 00/22] Add RZ/G3E GBETH support Pavel Machek
@ 2025-11-06 19:11 ` Pavel Machek
23 siblings, 0 replies; 33+ messages in thread
From: Pavel Machek @ 2025-11-06 19:11 UTC (permalink / raw)
To: John Madieu; +Cc: cip-dev, Nobuhiro Iwamatsu
[-- Attachment #1: Type: text/plain, Size: 426 bytes --]
Hi!
> Add RZ/G3E GBETH support to cip-6.12. While at it, also backport RZ/V2N Pinctrl and
> OEN dependencies.
Thank you, applied.
> Lad Prabhakar (11):
> soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
As discussed, I dropped this one.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread