* [PATCH 6.1.y-cip 1/9] dt-bindings: usb: renesas,usbhs: Add RZ/V2H(P) SoC support
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 2/9] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset Ovidiu Panait
` (9 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit c0a1d1e9a48f36086ef5a2863844175476bd3b8e upstream.
Document the Renesas USBHS controller found on the Renesas RZ/V2H(P) SoC.
The USBHS block on RZ/V2H(P) is functionally identical to the one on the
RZ/G2L family, so no driver changes are needed. The existing
"renesas,rzg2l-usbhs" fallback compatible will continue to be used for
handling this IP.
In addition, update the schema validation logic by replacing the enum list
of SoC-specific compatibles with a const "renesas,rzg2l-usbhs" as all
listed SoCs share identical USBHS hardware and already include the fallback
compatible. This will help to simplify the schema and avoid redundancy.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414165201.362262-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index c63db3ebd07b..45d133253094 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -26,6 +26,7 @@ properties:
- renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- renesas,usbhs-r9a07g054 # RZ/V2L
+ - renesas,usbhs-r9a09g057 # RZ/V2H(P)
- const: renesas,rzg2l-usbhs
- items:
@@ -122,10 +123,7 @@ allOf:
properties:
compatible:
contains:
- enum:
- - renesas,usbhs-r9a07g043
- - renesas,usbhs-r9a07g044
- - renesas,usbhs-r9a07g054
+ const: renesas,rzg2l-usbhs
then:
properties:
interrupts:
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 2/9] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 1/9] dt-bindings: usb: renesas,usbhs: Add RZ/V2H(P) SoC support Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 3/9] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) Ovidiu Panait
` (8 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 261f3ff29a2b15ad70bf2530550421ad9a9a5966 upstream.
Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset
controller. This block manages the reset and power-down of the USB 2.0 PHY,
which is used in both host and function modes.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../reset/renesas,rzv2h-usb2phy-reset.yaml | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
new file mode 100644
index 000000000000..c79f61c2373b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzv2h-usb2phy-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) USB2PHY Port reset Control
+
+maintainers:
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+ The RZ/V2H(P) USB2PHY Control mainly controls Port reset and power down of the
+ USB2.0 PHY.
+
+properties:
+ compatible:
+ const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
+
+ reset-controller@15830000 {
+ compatible = "renesas,r9a09g057-usb2phy-reset";
+ reg = <0x15830000 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb6>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ };
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 3/9] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 1/9] dt-bindings: usb: renesas,usbhs: Add RZ/V2H(P) SoC support Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 2/9] dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-21 13:28 ` [cip-dev] " Pavel Machek
2025-11-20 16:57 ` [PATCH 6.1.y-cip 4/9] dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family Ovidiu Panait
` (7 subsequent siblings)
10 siblings, 1 reply; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit e3911d7f865bbc704205f45333e491e4034942c7 upstream.
Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
Enable control of USB2.0 PHY reset and power-down operations, including
assert and deassert functionalities for the PHY.
Leverage device tree (OF) data to support future SoCs with similar USB2PHY
hardware but varying register configurations. Define initialization values
and control register settings to ensure flexibility for upcoming platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[OP: - added linux/of_device.h include
- replaced devm_reset_control_get_shared_deasserted() with
devm_reset_control_get_shared() + reset_control_deassert()
- added error handling in probe to assert the reset on errors
- added remove callback]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-rzv2h-usb2phy.c | 270 ++++++++++++++++++++++++++++
3 files changed, 278 insertions(+)
create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c561a93af655..e7ff064709cb 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -195,6 +195,13 @@ config RESET_RZG2L_USBPHY_CTRL
Support for USBPHY Control found on RZ/G2L family. It mainly
controls reset and power down of the USB/PHY.
+config RESET_RZV2H_USB2PHY
+ tristate "Renesas RZ/V2H(P) (and similar SoCs) USB2PHY Reset driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ help
+ Support for USB2PHY Port reset Control found on the RZ/V2H(P) SoC
+ (and similar SoCs).
+
config RESET_SCMI
tristate "Reset driver controlled via ARM SCMI interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e7e5fd633a8..970b085faca2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-rzv2h-usb2phy.c b/drivers/reset/reset-rzv2h-usb2phy.c
new file mode 100644
index 000000000000..a350afb5ae65
--- /dev/null
+++ b/drivers/reset/reset-rzv2h-usb2phy.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) USB2PHY Port reset control driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+
+struct rzv2h_usb2phy_regval {
+ u16 reg;
+ u16 val;
+};
+
+struct rzv2h_usb2phy_reset_of_data {
+ const struct rzv2h_usb2phy_regval *init_vals;
+ unsigned int init_val_count;
+
+ u16 reset_reg;
+ u16 reset_assert_val;
+ u16 reset_deassert_val;
+ u16 reset_status_bits;
+ u16 reset_release_val;
+
+ u16 reset2_reg;
+ u16 reset2_acquire_val;
+ u16 reset2_release_val;
+};
+
+struct rzv2h_usb2phy_reset_priv {
+ const struct rzv2h_usb2phy_reset_of_data *data;
+ void __iomem *base;
+ struct device *dev;
+ struct reset_control *rstc;
+ struct reset_controller_dev rcdev;
+ spinlock_t lock; /* protects register accesses */
+};
+
+static inline struct rzv2h_usb2phy_reset_priv
+*rzv2h_usbphy_rcdev_to_priv(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct rzv2h_usb2phy_reset_priv, rcdev);
+}
+
+/* This function must be called only after pm_runtime_resume_and_get() has been called */
+static void rzv2h_usbphy_assert_helper(struct rzv2h_usb2phy_reset_priv *priv)
+{
+ const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
+
+ scoped_guard(spinlock, &priv->lock) {
+ writel(data->reset2_acquire_val, priv->base + data->reset2_reg);
+ writel(data->reset_assert_val, priv->base + data->reset_reg);
+ }
+
+ usleep_range(11, 20);
+}
+
+static int rzv2h_usbphy_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+ struct device *dev = priv->dev;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ dev_err(dev, "pm_runtime_resume_and_get failed\n");
+ return ret;
+ }
+
+ rzv2h_usbphy_assert_helper(priv);
+
+ pm_runtime_put(dev);
+
+ return 0;
+}
+
+static int rzv2h_usbphy_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+ const struct rzv2h_usb2phy_reset_of_data *data = priv->data;
+ struct device *dev = priv->dev;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ dev_err(dev, "pm_runtime_resume_and_get failed\n");
+ return ret;
+ }
+
+ scoped_guard(spinlock, &priv->lock) {
+ writel(data->reset_deassert_val, priv->base + data->reset_reg);
+ writel(data->reset2_release_val, priv->base + data->reset2_reg);
+ writel(data->reset_release_val, priv->base + data->reset_reg);
+ }
+
+ pm_runtime_put(dev);
+
+ return 0;
+}
+
+static int rzv2h_usbphy_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzv2h_usb2phy_reset_priv *priv = rzv2h_usbphy_rcdev_to_priv(rcdev);
+ struct device *dev = priv->dev;
+ int ret;
+ u32 reg;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret) {
+ dev_err(dev, "pm_runtime_resume_and_get failed\n");
+ return ret;
+ }
+
+ reg = readl(priv->base + priv->data->reset_reg);
+
+ pm_runtime_put(dev);
+
+ return (reg & priv->data->reset_status_bits) == priv->data->reset_status_bits;
+}
+
+static const struct reset_control_ops rzv2h_usbphy_reset_ops = {
+ .assert = rzv2h_usbphy_reset_assert,
+ .deassert = rzv2h_usbphy_reset_deassert,
+ .status = rzv2h_usbphy_reset_status,
+};
+
+static int rzv2h_usb2phy_reset_of_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ /* No special handling needed, we have only one reset line per device */
+ return 0;
+}
+
+static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
+{
+ const struct rzv2h_usb2phy_reset_of_data *data;
+ struct rzv2h_usb2phy_reset_priv *priv;
+ struct device *dev = &pdev->dev;
+ int error;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ data = of_device_get_match_data(dev);
+ priv->data = data;
+ priv->dev = dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->rstc = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return dev_err_probe(dev, PTR_ERR(priv->rstc),
+ "failed to get reset\n");
+
+ error = reset_control_deassert(priv->rstc);
+ if (error)
+ return dev_err_probe(dev, error,
+ "failed to deassert reset\n");
+
+ spin_lock_init(&priv->lock);
+
+ error = devm_pm_runtime_enable(dev);
+ if (error) {
+ dev_err_probe(dev, error, "Failed to enable pm_runtime\n");
+ goto out_assert_rst;
+ }
+
+ error = pm_runtime_resume_and_get(dev);
+ if (error) {
+ dev_err_probe(dev, error, "pm_runtime_resume_and_get failed\n");
+ goto out_assert_rst;
+ }
+
+ for (unsigned int i = 0; i < data->init_val_count; i++)
+ writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg);
+
+ /* keep usb2phy in asserted state */
+ rzv2h_usbphy_assert_helper(priv);
+
+ pm_runtime_put(dev);
+
+ priv->rcdev.ops = &rzv2h_usbphy_reset_ops;
+ priv->rcdev.of_reset_n_cells = 0;
+ priv->rcdev.nr_resets = 1;
+ priv->rcdev.of_xlate = rzv2h_usb2phy_reset_of_xlate;
+ priv->rcdev.of_node = dev->of_node;
+ priv->rcdev.dev = dev;
+
+ platform_set_drvdata(pdev, priv);
+
+ error = devm_reset_controller_register(dev, &priv->rcdev);
+ if (error) {
+ dev_err_probe(dev, error,
+ "devm_reset_controller_register() failed");
+ goto out_assert_rst;
+ }
+
+ return 0;
+
+out_assert_rst:
+ reset_control_assert(priv->rstc);
+
+ return error;
+}
+
+static int rzv2h_usb2phy_reset_remove(struct platform_device *pdev)
+{
+ struct rzv2h_usb2phy_reset_priv *priv = platform_get_drvdata(pdev);
+
+ reset_control_assert(priv->rstc);
+
+ return 0;
+}
+
+/*
+ * initialization values required to prepare the PHY to receive
+ * assert and deassert requests.
+ */
+static const struct rzv2h_usb2phy_regval rzv2h_init_vals[] = {
+ { .reg = 0xc10, .val = 0x67c },
+ { .reg = 0xc14, .val = 0x1f },
+ { .reg = 0x600, .val = 0x909 },
+};
+
+static const struct rzv2h_usb2phy_reset_of_data rzv2h_reset_of_data = {
+ .init_vals = rzv2h_init_vals,
+ .init_val_count = ARRAY_SIZE(rzv2h_init_vals),
+ .reset_reg = 0,
+ .reset_assert_val = 0x206,
+ .reset_status_bits = BIT(2),
+ .reset_deassert_val = 0x200,
+ .reset_release_val = 0x0,
+ .reset2_reg = 0xb04,
+ .reset2_acquire_val = 0x303,
+ .reset2_release_val = 0x3,
+};
+
+static const struct of_device_id rzv2h_usb2phy_reset_of_match[] = {
+ { .compatible = "renesas,r9a09g057-usb2phy-reset", .data = &rzv2h_reset_of_data },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzv2h_usb2phy_reset_of_match);
+
+static struct platform_driver rzv2h_usb2phy_reset_driver = {
+ .driver = {
+ .name = "rzv2h_usb2phy_reset",
+ .of_match_table = rzv2h_usb2phy_reset_of_match,
+ },
+ .probe = rzv2h_usb2phy_reset_probe,
+ .remove = rzv2h_usb2phy_reset_remove,
+};
+module_platform_driver(rzv2h_usb2phy_reset_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/V2H(P) USB2PHY Control");
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 3/9] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 3/9] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) Ovidiu Panait
@ 2025-11-21 13:28 ` Pavel Machek
0 siblings, 0 replies; 14+ messages in thread
From: Pavel Machek @ 2025-11-21 13:28 UTC (permalink / raw)
To: ovidiu.panait.rb, prabhakar.mahadev-lad.rj; +Cc: cip-dev, nobuhiro1.iwamatsu
[-- Attachment #1: Type: text/plain, Size: 1356 bytes --]
Hi!
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> commit e3911d7f865bbc704205f45333e491e4034942c7 upstream.
>
> Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
> Enable control of USB2.0 PHY reset and power-down operations, including
> assert and deassert functionalities for the PHY.
>
> Leverage device tree (OF) data to support future SoCs with similar USB2PHY
> hardware but varying register configurations. Define initialization values
> and control register settings to ensure flexibility for upcoming
> platforms.
> +static int rzv2h_usb2phy_reset_probe(struct platform_device *pdev)
> +{
> + const struct rzv2h_usb2phy_reset_of_data *data;
> + struct rzv2h_usb2phy_reset_priv *priv;
> + struct device *dev = &pdev->dev;
> + int error;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + data = of_device_get_match_data(dev);
> + priv->data = data;
> + priv->dev = dev;
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
Should this be dev_err_probe, so that user gets error message?
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6.1.y-cip 4/9] dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (2 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 3/9] reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P) Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 5/9] dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC Ovidiu Panait
` (6 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 31eebeef8cdd4c9bddc9d34053cab6553616d0b7 upstream.
The RZ/G2L family requires two clocks for USB2 PHY, which are already
defined in the DTSI files. Add a constraint in the DT binding document
to ensure validation with `dtbs_check`.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index f82649a55e91..af9ed41c00c5 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -105,6 +105,9 @@ allOf:
contains:
const: renesas,rzg2l-usb2-phy
then:
+ properties:
+ clocks:
+ minItems: 2
required:
- resets
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 5/9] dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (3 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 4/9] dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 6/9] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P) Ovidiu Panait
` (5 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 9c4fbefc962dd13694b4a5051f432ed435c92220 upstream.
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC.
RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it
needs additional configuration to be done as compared RZ/G2L USB2.0 phy.
To handle this difference a SoC specific compat string is added for
RZ/V2H(P) SoC.
Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets`
property and has two clocks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../devicetree/bindings/phy/renesas,usb2-phy.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index af9ed41c00c5..131314066e3a 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -13,7 +13,9 @@ properties:
compatible:
oneOf:
- items:
- - const: renesas,usb2-phy-r8a77470 # RZ/G1C
+ - enum:
+ - renesas,usb2-phy-r8a77470 # RZ/G1C
+ - renesas,usb2-phy-r9a09g057 # RZ/V2H(P)
- items:
- enum:
@@ -103,7 +105,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,rzg2l-usb2-phy
+ enum:
+ - renesas,usb2-phy-r9a09g057
+ - renesas,rzg2l-usb2-phy
then:
properties:
clocks:
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 6/9] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P)
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (4 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 5/9] dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 7/9] arm64: dts: renesas: r9a09g057: Add USB2.0 support Ovidiu Panait
` (4 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 3767474d7497a4d03f58118d02b742b903626d03 upstream.
Add USB2.0 PHY support for RZ/V2H(P) SoC.
On the RZ/V2H(P) SoC we need to configure the UTMI to a specific value
as compared to other SoCs (which doesn't need configuring it).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250414145729.343133-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 30 ++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index ccf7bb3885d6..fc52f7685d63 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -31,8 +31,10 @@
#define USB2_INT_ENABLE 0x000
#define USB2_AHB_BUS_CTR 0x008
#define USB2_USBCTR 0x00c
+#define USB2_REGEN_CG_CTRL 0x104 /* RZ/V2H(P) only */
#define USB2_SPD_RSM_TIMSET 0x10c
#define USB2_OC_TIMSET 0x110
+#define USB2_UTMI_CTRL 0x118 /* RZ/V2H(P) only */
#define USB2_COMMCTRL 0x600
#define USB2_OBINTSTA 0x604
#define USB2_OBINTEN 0x608
@@ -53,12 +55,18 @@
#define USB2_USBCTR_DIRPD BIT(2)
#define USB2_USBCTR_PLL_RST BIT(1)
+/* REGEN_CG_CTRL*/
+#define USB2_REGEN_CG_CTRL_UPHY_WEN BIT(0)
+
/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT 0x000209ab
+/* UTMI_CTRL */
+#define USB2_UTMI_CTRL_INIT 0x8000018f
+
/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
@@ -128,12 +136,14 @@ struct rcar_gen3_chan {
bool is_otg_channel;
bool uses_otg_pins;
bool soc_no_adp_ctrl;
+ bool utmi_ctrl;
};
struct rcar_gen3_phy_drv_data {
const struct phy_ops *phy_usb2_ops;
bool no_adp_ctrl;
bool init_bus;
+ bool utmi_ctrl;
};
/*
@@ -479,6 +489,14 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
if (rphy->int_enable_bits)
rcar_gen3_init_otg(channel);
+ if (channel->utmi_ctrl) {
+ val = readl(usb2_base + USB2_REGEN_CG_CTRL) | USB2_REGEN_CG_CTRL_UPHY_WEN;
+ writel(val, usb2_base + USB2_REGEN_CG_CTRL);
+
+ writel(USB2_UTMI_CTRL_INIT, usb2_base + USB2_UTMI_CTRL);
+ writel(val & ~USB2_REGEN_CG_CTRL_UPHY_WEN, usb2_base + USB2_REGEN_CG_CTRL);
+ }
+
rphy->initialized = true;
return 0;
@@ -588,6 +606,12 @@ static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
.no_adp_ctrl = true,
};
+static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data = {
+ .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+ .no_adp_ctrl = true,
+ .utmi_ctrl = true,
+};
+
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
{
.compatible = "renesas,usb2-phy-r8a77470",
@@ -605,6 +629,10 @@ static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
.compatible = "renesas,usb2-phy-r8a77965",
.data = &rcar_gen3_phy_usb2_data,
},
+ {
+ .compatible = "renesas,usb2-phy-r9a09g057",
+ .data = &rz_v2h_phy_usb2_data,
+ },
{
.compatible = "renesas,rzg2l-usb2-phy",
.data = &rz_g2l_phy_usb2_data,
@@ -756,6 +784,8 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (phy_data->no_adp_ctrl)
channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+ channel->utmi_ctrl = phy_data->utmi_ctrl;
+
spin_lock_init(&channel->lock);
for (i = 0; i < NUM_OF_PHYS; i++) {
channel->rphys[i].phy = devm_phy_create(dev, NULL,
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 7/9] arm64: dts: renesas: r9a09g057: Add USB2.0 support
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (5 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 6/9] phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P) Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 8/9] arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver Ovidiu Panait
` (3 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 3cbd627482eabf185893c265dc9ae7c0a1ef24e5 upstream.
The Renesas RZ/V2H(P) ("R9A09G057") SoC supports 1x channel with OTG/DRD
and 1x channel with host interface.
Add the ECHI, OHCI, USB2.0 PHY and reset control nodes for USB2.0
channels in R9A09G057 SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515183104.330964-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 113 +++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 2e2d8ed42e6d..24a5356f8074 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -591,6 +591,119 @@ gic: interrupt-controller@14900000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ ohci0: usb@15800000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15800000 0 0x100>;
+ interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@15810000 {
+ compatible = "generic-ohci";
+ reg = <0 0x15810000 0 0x100>;
+ interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@15800100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15800100 0 0x100>;
+ interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
+ resets = <&usb20phyrst>, <&cpg 0xac>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@15810100 {
+ compatible = "generic-ehci";
+ reg = <0 0x15810100 0 0x100>;
+ interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
+ resets = <&usb21phyrst>, <&cpg 0xad>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@15800200 {
+ compatible = "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15800200 0 0x700>;
+ interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>,
+ <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb20phyrst>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@15810200 {
+ compatible = "renesas,usb2-phy-r9a09g057";
+ reg = <0 0x15810200 0 0x700>;
+ interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb4>,
+ <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>;
+ clock-names = "fck", "usb_x1";
+ resets = <&usb21phyrst>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ hsusb: usb@15820000 {
+ compatible = "renesas,usbhs-r9a09g057",
+ "renesas,rzg2l-usbhs";
+ reg = <0 0x15820000 0 0x10000>;
+ interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
+ resets = <&usb20phyrst>,
+ <&cpg 0xae>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb20phyrst: usb20phy-reset@15830000 {
+ compatible = "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15830000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb6>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ status = "disabled";
+ };
+
+ usb21phyrst: usb21phy-reset@15840000 {
+ compatible = "renesas,r9a09g057-usb2phy-reset";
+ reg = <0 0x15840000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb7>;
+ resets = <&cpg 0xaf>;
+ power-domains = <&cpg>;
+ #reset-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 8/9] arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (6 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 7/9] arm64: dts: renesas: r9a09g057: Add USB2.0 support Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-20 16:57 ` [PATCH 6.1.y-cip 9/9] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support Ovidiu Panait
` (2 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 41cffe6d234617f9637b68209a4ee42e0457f2a3 upstream.
Enable the `CONFIG_RESET_RZV2H_USB2PHY` option in the arm64 defconfig to
support the USB2 PHY controller reset driver on the Renesas RZ/V2H(P)
SoC, as used on the RZ/V2H EVK board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513125858.251064-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0b36ee0b963c..4c1305008789 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1240,6 +1240,7 @@ CONFIG_RESET_IMX7=y
CONFIG_RESET_QCOM_AOSS=y
CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
+CONFIG_RESET_RZV2H_USB2PHY=m
CONFIG_RESET_TI_SCI=y
CONFIG_PHY_XGENE=y
CONFIG_PHY_CAN_TRANSCEIVER=m
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6.1.y-cip 9/9] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (7 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 8/9] arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver Ovidiu Panait
@ 2025-11-20 16:57 ` Ovidiu Panait
2025-11-22 9:05 ` [cip-dev] [PATCH 6.1.y-cip 0/9] Add RZ/V2H " Pavel Machek
2025-11-24 0:08 ` Nobuhiro Iwamatsu (Toshiba)
10 siblings, 0 replies; 14+ messages in thread
From: Ovidiu Panait @ 2025-11-20 16:57 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro1.iwamatsu
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 46d5ca6521dee03cf66b2ed54709112053e94c35 upstream.
Enable USB2.0 support on the RZ/V2H EVK board, CN3 supports
host only operation and CN2 supports host/function operation.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515183104.330964-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250613152216.201957-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 392fd2a54649..81b9bcbd440b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -79,6 +79,15 @@ &audio_extal_clk {
clock-frequency = <22579200>;
};
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
ð0 {
pinctrl-0 = <ð0_pins>;
pinctrl-names = "default";
@@ -95,6 +104,11 @@ ð1 {
status = "okay";
};
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -189,6 +203,15 @@ phy1: ethernet-phy@1 {
};
};
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
&ostm0 {
status = "okay";
};
@@ -297,6 +320,26 @@ sd1_cd {
pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
};
};
+
+ usb20_pins: usb20 {
+ ovc {
+ pinmux = <RZV2H_PORT_PINMUX(9, 6, 14)>; /* OVC */
+ };
+
+ vbus {
+ pinmux = <RZV2H_PORT_PINMUX(9, 5, 14)>; /* VBUS */
+ };
+ };
+
+ usb21_pins: usb21 {
+ ovc {
+ pinmux = <RZV2H_PORT_PINMUX(6, 7, 14)>; /* OVC */
+ };
+
+ vbus {
+ pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */
+ };
+ };
};
&qextal_clk {
@@ -326,6 +369,28 @@ &sdhi1 {
status = "okay";
};
+&usb20phyrst {
+ status = "okay";
+};
+
+&usb21phyrst {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb20_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb21_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&wdt1 {
status = "okay";
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (8 preceding siblings ...)
2025-11-20 16:57 ` [PATCH 6.1.y-cip 9/9] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support Ovidiu Panait
@ 2025-11-22 9:05 ` Pavel Machek
2025-11-24 0:08 ` Nobuhiro Iwamatsu (Toshiba)
10 siblings, 0 replies; 14+ messages in thread
From: Pavel Machek @ 2025-11-22 9:05 UTC (permalink / raw)
To: ovidiu.panait.rb; +Cc: cip-dev, nobuhiro1.iwamatsu
[-- Attachment #1: Type: text/plain, Size: 441 bytes --]
Hi!
> This series adds USB2.0 support for the Renesas RZ/V2H SoC.
>
> Patches were cherry-picked from mainline kernel.
Series looks good to me. I can apply it if there are no other comments
and it passes testing.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support
2025-11-20 16:57 [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support Ovidiu Panait
` (9 preceding siblings ...)
2025-11-22 9:05 ` [cip-dev] [PATCH 6.1.y-cip 0/9] Add RZ/V2H " Pavel Machek
@ 2025-11-24 0:08 ` Nobuhiro Iwamatsu (Toshiba)
2025-11-24 9:59 ` Pavel Machek
10 siblings, 1 reply; 14+ messages in thread
From: Nobuhiro Iwamatsu (Toshiba) @ 2025-11-24 0:08 UTC (permalink / raw)
To: ovidiu.panait.rb; +Cc: cip-dev, pavel, nobuhiro1.iwamatsu
Hi all,
2025年11月21日(金) 1:57 Ovidiu Panait via lists.cip-project.org
<ovidiu.panait.rb=renesas.com@lists.cip-project.org>:
>
> Hi,
>
> This series adds USB2.0 support for the Renesas RZ/V2H SoC.
>
> Patches were cherry-picked from mainline kernel.
>
> Best regards,
> Ovidiu
>
> Lad Prabhakar (9):
> dt-bindings: usb: renesas,usbhs: Add RZ/V2H(P) SoC support
> dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
> reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
> dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L
> family
> dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
> phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P)
> arm64: dts: renesas: r9a09g057: Add USB2.0 support
> arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver
> arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
>
> .../bindings/phy/renesas,usb2-phy.yaml | 11 +-
> .../reset/renesas,rzv2h-usb2phy-reset.yaml | 56 ++++
> .../bindings/usb/renesas,usbhs.yaml | 6 +-
> arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 113 ++++++++
> .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 65 +++++
> arch/arm64/configs/defconfig | 1 +
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 30 ++
> drivers/reset/Kconfig | 7 +
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-rzv2h-usb2phy.c | 270 ++++++++++++++++++
> 10 files changed, 554 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml
> create mode 100644 drivers/reset/reset-rzv2h-usb2phy.c
>
Looks good to me, I can apply this series if there are no other comments.
Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 0/9] Add RZ/V2H USB2.0 support
2025-11-24 0:08 ` Nobuhiro Iwamatsu (Toshiba)
@ 2025-11-24 9:59 ` Pavel Machek
0 siblings, 0 replies; 14+ messages in thread
From: Pavel Machek @ 2025-11-24 9:59 UTC (permalink / raw)
To: iwamatsu; +Cc: ovidiu.panait.rb, cip-dev, nobuhiro1.iwamatsu
[-- Attachment #1: Type: text/plain, Size: 673 bytes --]
Hi!
> > This series adds USB2.0 support for the Renesas RZ/V2H SoC.
> >
> > Patches were cherry-picked from mainline kernel.
>
> Looks good to me, I can apply this series if there are no other comments.
>
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
Thank you, applied and pushed out.
I'm getting problems testing this, but I believe they are caused by
not enough boards in the test labs.
https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2173447147
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 14+ messages in thread