[PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[Ovidiu Panait]

Hi,

This series adds watchdog timer support for the Renesas RZ/V2N SoC.

Patches were cherry-picked from mainline kernel.

Best regards,
Ovidiu

Lad Prabhakar (4):
  dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
    support
  clk: renesas: r9a09g056: Add clock and reset entries for WDT
    controllers
  arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
  arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1

 .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40 +++++++++++++++++++
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
 drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
 4 files changed, 67 insertions(+), 1 deletion(-)

-- 
2.51.0

[PATCH 6.12.y-cip 1/4] dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056) support

[Ovidiu Panait]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit f55937e42c9951b615e291d9b7e6337747804463 upstream.

Document support for the watchdog IP found on the Renesas RZ/V2N
(R9A09G056) SoC. The watchdog IP is identical to that on RZ/V2H(P),
so `renesas,r9a09g057-wdt` will be used as a fallback compatible,
enabling reuse of the existing driver without changes.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20250502120054.47323-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
index 3e0a8747a357..78874b90c88c 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
@@ -76,7 +76,9 @@ properties:
           - const: renesas,rcar-gen4-wdt # R-Car Gen4
 
       - items:
-          - const: renesas,r9a09g047-wdt # RZ/G3E
+          - enum:
+              - renesas,r9a09g047-wdt # RZ/G3E
+              - renesas,r9a09g056-wdt # RZ/V2N
           - const: renesas,r9a09g057-wdt # RZ/V2H(P)
 
       - const: renesas,r9a09g057-wdt       # RZ/V2H(P)
-- 
2.51.0

[PATCH 6.12.y-cip 2/4] clk: renesas: r9a09g056: Add clock and reset entries for WDT controllers

[Ovidiu Panait]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit e018f9f8973760faacbdf9bf678fdb46c1f591c8 upstream.

Add module clock and reset definitions for WDT0-3, which are available
on the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/clk/renesas/r9a09g056-cpg.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 5cabaa3237eb..e4c1c74f56b5 100644
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -112,6 +112,22 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
 						BUS_MSTOP(11, BIT(15))),
 	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,
 						BUS_MSTOP(12, BIT(0))),
+	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,
+						BUS_MSTOP(3, BIT(10))),
+	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,
+						BUS_MSTOP(3, BIT(10))),
+	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
+						BUS_MSTOP(1, BIT(0))),
+	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
+						BUS_MSTOP(1, BIT(0))),
+	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,
+						BUS_MSTOP(5, BIT(12))),
+	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,
+						BUS_MSTOP(5, BIT(12))),
+	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
+						BUS_MSTOP(5, BIT(13))),
+	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
+						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
 						BUS_MSTOP(3, BIT(14))),
 	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
@@ -152,6 +168,10 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
 	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */
 	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */
 	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */
+	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */
+	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
+	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
+	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
 	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
-- 
2.51.0

[PATCH 6.12.y-cip 3/4] arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes

[Ovidiu Panait]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit 7db958983c8dd14d65efdf64dd9cdcd9ce2ad2c6 upstream.

Add WDT0-WDT3 nodes to RZ/V2N ("R9A09G056") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514101528.41663-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 64420fbdf959..068f966d571c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -257,6 +257,46 @@ ostm7: timer@12c03000 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@11c00400 {
+			compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x11c00400 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x75>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@14400000 {
+			compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x14400000 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x76>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@13000000 {
+			compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x13000000 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x77>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@13000400 {
+			compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt";
+			reg = <0 0x13000400 0 0x400>;
+			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 0x78>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		scif: serial@11c01400 {
 			compatible = "renesas,scif-r9a09g056",
 				     "renesas,scif-r9a09g057";
-- 
2.51.0

[PATCH 6.12.y-cip 4/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1

[Ovidiu Panait]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

commit f3e57b92340400e99d0b6341c40692c5cb5ab774 upstream.

Enable WDT1 hardware block on the RZ/V2N EVK.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514101528.41663-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
index d33a28521c9f..3e0606a8c034 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
@@ -153,3 +153,7 @@ &sdhi1 {
 	sd-uhs-sdr104;
 	status = "okay";
 };
+
+&wdt1 {
+	status = "okay";
+};
-- 
2.51.0

Re: [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[Nobuhiro Iwamatsu (Toshiba)]

H all,

2025年12月13日(土) 6:38 Ovidiu Panait via lists.cip-project.org
<ovidiu.panait.rb=renesas.com@lists.cip-project.org>:
>
> Hi,
>
> This series adds watchdog timer support for the Renesas RZ/V2N SoC.
>
> Patches were cherry-picked from mainline kernel.
>
> Best regards,
> Ovidiu
>
> Lad Prabhakar (4):
>   dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
>     support
>   clk: renesas: r9a09g056: Add clock and reset entries for WDT
>     controllers
>   arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
>   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
>
>  .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
>  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40 +++++++++++++++++++
>  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
>  drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
>  4 files changed, 67 insertions(+), 1 deletion(-)
>

I reviewed this series, and it looks good to me.
I can apply to this series if there are no other comments.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

Best regards,
  Nobuhiro

-- 
Nobuhiro Iwamatsu

Re: [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1120 bytes --]

Hi!

> > Lad Prabhakar (4):
> >   dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
> >     support
> >   clk: renesas: r9a09g056: Add clock and reset entries for WDT
> >     controllers
> >   arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
> >   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
> >
> >  .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
> >  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40 +++++++++++++++++++
> >  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
> >  drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
> >  4 files changed, 67 insertions(+), 1 deletion(-)
> >
> 
> I reviewed this series, and it looks good to me.
> I can apply to this series if there are no other comments.
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

It looks good to me, too, and it passed testing, so I'm adding your
reviewed-by and pushing the result.

Thank you,
								Pavel
-- 
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[nobuhiro.iwamatsu.x90]

Hi Ovidiu,

Could you rebase to HEAD of each branches (6.1.y-cip and 6.12.y-cip), and resend ?
I can not apply to each HEAD.

Best regards,
  Nobuhiro

> -----Original Message-----
> From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Sent: Saturday, December 13, 2025 6:39 AM
> To: cip-dev@lists.cip-project.org; pavel@denx.de; iwamatsu nobuhiro(岩松 信洋
> □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> Subject: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support
> 
> Hi,
> 
> This series adds watchdog timer support for the Renesas RZ/V2N SoC.
> 
> Patches were cherry-picked from mainline kernel.
> 
> Best regards,
> Ovidiu
> 
> Lad Prabhakar (4):
>   dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
>     support
>   clk: renesas: r9a09g056: Add clock and reset entries for WDT
>     controllers
>   arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
>   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
> 
>  .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
>  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40
> +++++++++++++++++++
>  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
>  drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
>  4 files changed, 67 insertions(+), 1 deletion(-)
> 
> --
> 2.51.0

RE: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[Ovidiu Panait]

Hi Nobuhiro-San,

> Hi Ovidiu,
> 
> Could you rebase to HEAD of each branches (6.1.y-cip and 6.12.y-cip), and
> resend ?
> I can not apply to each HEAD.
> 

Thanks for the heads up! It seems the WDT series were applied already to both
6.1-cip and 6.12-cip by Pavel, so no further action is needed.

Thanks!
Ovidiu


> Best regards,
>   Nobuhiro
> 
> > -----Original Message-----
> > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > Sent: Saturday, December 13, 2025 6:39 AM
> > To: cip-dev@lists.cip-project.org; pavel@denx.de; iwamatsu nobuhiro(岩松
> 信洋
> > □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> > Subject: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support
> >
> > Hi,
> >
> > This series adds watchdog timer support for the Renesas RZ/V2N SoC.
> >
> > Patches were cherry-picked from mainline kernel.
> >
> > Best regards,
> > Ovidiu
> >
> > Lad Prabhakar (4):
> >   dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
> >     support
> >   clk: renesas: r9a09g056: Add clock and reset entries for WDT
> >     controllers
> >   arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
> >   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
> >
> >  .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
> >  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40
> > +++++++++++++++++++
> >  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
> >  drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
> >  4 files changed, 67 insertions(+), 1 deletion(-)
> >
> > --
> > 2.51.0
> 

RE: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support

[nobuhiro.iwamatsu.x90]

Hi Ovidiu,

Sorry for reply was too late.

> -----Original Message-----
> From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Sent: Monday, December 29, 2025 5:52 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro.iwamatsu.x90@mail.toshiba>; cip-dev@lists.cip-project.org;
> pavel@denx.de
> Subject: RE: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support
> 
> Hi Nobuhiro-San,
> 
> > Hi Ovidiu,
> >
> > Could you rebase to HEAD of each branches (6.1.y-cip and 6.12.y-cip),
> > and resend ?
> > I can not apply to each HEAD.
> >
> 
> Thanks for the heads up! It seems the WDT series were applied already to both
> 6.1-cip and 6.12-cip by Pavel, so no further action is needed.

It was my fault, thank you for letting me know.

> 
> Thanks!
> Ovidiu
> 
Best regards,
  Nobuhiro

> >
> > > -----Original Message-----
> > > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > Sent: Saturday, December 13, 2025 6:39 AM
> > > To: cip-dev@lists.cip-project.org; pavel@denx.de; iwamatsu
> > > nobuhiro(岩松
> > 信洋
> > > □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> > > Subject: [PATCH 6.12.y-cip 0/4] Add RZ/V2N WDT support
> > >
> > > Hi,
> > >
> > > This series adds watchdog timer support for the Renesas RZ/V2N SoC.
> > >
> > > Patches were cherry-picked from mainline kernel.
> > >
> > > Best regards,
> > > Ovidiu
> > >
> > > Lad Prabhakar (4):
> > >   dt-bindings: watchdog: renesas,wdt: Document RZ/V2N (R9A09G056)
> > >     support
> > >   clk: renesas: r9a09g056: Add clock and reset entries for WDT
> > >     controllers
> > >   arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
> > >   arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
> > >
> > >  .../bindings/watchdog/renesas,wdt.yaml        |  4 +-
> > >  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 40
> > > +++++++++++++++++++
> > >  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    |  4 ++
> > >  drivers/clk/renesas/r9a09g056-cpg.c           | 20 ++++++++++
> > >  4 files changed, 67 insertions(+), 1 deletion(-)
> > >
> > > --
> > > 2.51.0
> >