[PATCH 6.12.y-cip 38/38] arm64: dts: renesas: rzt2h-n2h-evk-common: Add pinctrl for SCI0 node

Lad Prabhakar
2025-12-05T14:34:12Z

commit 1366c160df036d5596240ea4b36b88afe2cd0d2a upstream.

Add pinctrl for SCI0 node.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250820200659.2048755-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 66d97059c47c9..245b70f1557fe 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -23,6 +23,23 @@ &extal_clk {
clock-frequency = <25000000>;
};

+&pinctrl {
+ /*
+ * SCI0 Pin Configuration:
+ * ------------------------
+ * Signal | Pin | RZ/T2H (SW4) | RZ/N2H (DSW9)
+ * -----------|---------|--------------|---------------
+ * SCI0_RXD | P27_4 | 5: ON, 6: OFF| 1: ON, 2: OFF
+ * SCI0_TXD | P27_5 | 7: ON, 8: OFF| 3: ON, 4: OFF
+ */
+ sci0_pins: sci0-pins {
+ pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
+ <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
+ };
+};
+
&sci0 {
+ pinctrl-0 = <&sci0_pins>;
+ pinctrl-names = "default";
status = "okay";
};
--
2.43.0