From: Pavel Machek <pavel@denx.de>
To: Biju <biju.das.au@gmail.com>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 5.10.y-cip 0/3] Add 64-bit polling support
Date: Tue, 16 Dec 2025 11:25:13 +0100 [thread overview]
Message-ID: <aUEziZB2rbYEU3L1@duo.ucw.cz> (raw)
In-Reply-To: <20251215125316.137879-1-biju.das.jz@bp.renesas.com>
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Hi!
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.
This looks okay to me. I can apply it if it passes testing and there
are no other comments.
Best regards,
Pavel
--
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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next prev parent reply other threads:[~2025-12-16 10:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 12:52 [PATCH 5.10.y-cip 0/3] Add 64-bit polling support Biju
2025-12-15 12:53 ` [PATCH 5.10.y-cip 1/3] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode Biju
2025-12-15 12:53 ` [PATCH 5.10.y-cip 2/3] mmc: renesas_sdhi: Enable 64-bit " Biju
2025-12-15 12:53 ` [PATCH 5.10.y-cip 3/3] mmc: renesas_sdhi: Replace magic number '0xff' in renesas_sdhi_set_clock() Biju
2025-12-16 10:25 ` Pavel Machek [this message]
2025-12-16 13:09 ` [PATCH 5.10.y-cip 0/3] Add 64-bit polling support nobuhiro.iwamatsu.x90
2025-12-16 20:45 ` Pavel Machek
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