[PATCH 6.12.y-cip 0/5] Add gpio keys/sleep button support for RZ/G3E

[PATCH 6.12.y-cip 0/5] Add gpio keys/sleep button support for RZ/G3E

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add gpio keys support for waking up from s2idle and sleep button support
for entering to STR. Wakeup of STR is by pressing and holding power
button. All the patches in this series are cherry-picked from mainline.

STR logs:
root@smarc-rzg3e:~# [   25.082405] PM: suspend entry (deep)
[   25.086495] Filesystems sync: 0.000 seconds
[   25.098336] Freezing user space processes
[   25.104215] Freezing user space processes completed (elapsed 0.001 seconds)
[   25.111199] OOM killer disabled.
[   25.114443] Freezing remaining freezable tasks
[   25.120149] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
[   25.127557] printk: Suspending console(s) (use no_console_suspend to debug)
NOTICE:  BL2: v2.10.5(release):b288fa6dd
NOTICE:  BL2: Built : 11:10:41, Dec 11 2025
NOTICE:  BL2: SYS_LSI_MODE: 0x13e06
NOTICE:  BL2: SYS_LSI_DEVID: 0x8679447
NOTICE:  BL2: SYS_LSI_PRR: 0x0
NOTICE:  BL2: Booting BL31
[   25.179095] renesas-gbeth 15c30000.ethernet end0: Link is Down
[   25.186526] Disabling non-boot CPUs ...
[   25.189612] psci: CPU3 killed (polled 4 ms)
[   25.196378] psci: CPU2 killed (polled 0 ms)
[   25.202614] psci: CPU1 killed (polled 0 ms)
[   25.209180] Enabling non-boot CPUs ...
[   25.209374] Detected VIPT I-cache on CPU1
[   25.209419] GICv3: CPU1: found redistributor 100 region 0:0x0000000014960000
[   25.209457] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[   25.209990] CPU1 is up
[   25.210078] Detected VIPT I-cache on CPU2
[   25.210099] GICv3: CPU2: found redistributor 200 region 0:0x0000000014980000
[   25.210119] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[   25.210484] CPU2 is up
[   25.210573] Detected VIPT I-cache on CPU3
[   25.210594] GICv3: CPU3: found redistributor 300 region 0:0x00000000149a0000
[   25.210614] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[   25.211104] CPU3 is up
[   25.212242] renesas-gbeth 15c30000.ethernet end0: configuring for phy/rgmii-id link mode
[   25.225378] dwmac4: Master AXI performs any burst length
[   25.225409] renesas-gbeth 15c30000.ethernet end0: No Safety Features support found
[   25.225427] renesas-gbeth 15c30000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
[   25.225572] renesas-gbeth 15c40000.ethernet end1: configuring for phy/rgmii-id link mode
[   25.237367] dwmac4: Master AXI performs any burst length
[   25.237394] renesas-gbeth 15c40000.ethernet end1: No Safety Features support found
[   25.237408] renesas-gbeth 15c40000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
[   25.430129] OOM killer enabled.
[   25.433255] Restarting tasks ... done.
[   25.437594] random: crng reseeded on system resumption
[   25.442833] PM: suspend exit

root@smarc-rzg3e:~#

s2idle logs:
root@smarc-rzg3e:~# echo freeze > /sys/power/state
[   49.646154] PM: suspend entry (s2idle)
[   49.660843] Filesystems sync: 0.010 seconds
[   49.670380] Freezing user space processes
[   49.676749] Freezing user space processes completed (elapsed 0.002 seconds)
[   49.683897] OOM killer disabled.
[   49.687248] Freezing remaining freezable tasks
[   49.693235] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
[   49.700799] printk: Suspending console(s) (use no_console_suspend to debug)
[   49.735926] renesas-gbeth 15c30000.ethernet end0: Link is Down
[   51.619991] renesas-gbeth 15c30000.ethernet end0: configuring for phy/rgmii-id link mode
[   51.635772] dwmac4: Master AXI performs any burst length
[   51.635852] renesas-gbeth 15c30000.ethernet end0: No Safety Features support found
[   51.635912] renesas-gbeth 15c30000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
[   51.636252] renesas-gbeth 15c40000.ethernet end1: configuring for phy/rgmii-id link mode
[   51.652051] dwmac4: Master AXI performs any burst length
[   51.652126] renesas-gbeth 15c40000.ethernet end1: No Safety Features support found
[   51.652181] renesas-gbeth 15c40000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
[   51.765175] OOM killer enabled.
[   51.768332] Restarting tasks ... done.
[   51.773325] random: crng reseeded on system resumption
[   51.778619] PM: suspend exit

Biju Das (4):
  pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt
    control registers
  pinctrl: renesas: rzg2l: Drop unnecessary pin configurations
  arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
  arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI
    function

Lad Prabhakar (1):
  pinctrl: renesas: rzg2l: Validate pins before setting mux function

 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 38 +++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 31 +++++++
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       | 82 +++++++++++++------
 3 files changed, 124 insertions(+), 27 deletions(-)

-- 
2.43.0

[PATCH 6.12.y-cip 1/5] pinctrl: renesas: rzg2l: Validate pins before setting mux function

[Biju]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

[ Upstream commit 52161035571cd62be9865039b4be65615860dce0 ]

Ensure only valid pins are configured by validating pin mappings before
setting the mux function.

Rename rzg2l_validate_gpio_pin() to rzg2l_validate_pin() to reflect its
broader purpose validating both GPIO pins and muxed pins. This helps
avoid invalid configurations.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250616132750.216368-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 45 ++++++++++++++-----------
 1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 1ea2dc1608b3..a8887acfdef8 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -518,6 +518,23 @@ static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
 	writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
 }
 
+static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,
+			      u64 cfg, u32 port, u8 bit)
+{
+	u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
+	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
+	u64 data;
+
+	if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
+		return -EINVAL;
+
+	data = pctrl->data->port_pin_configs[port];
+	if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
+		return -EINVAL;
+
+	return 0;
+}
+
 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 				       u8 pin, u8 off, u8 func)
 {
@@ -561,6 +578,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 	unsigned int i, *psel_val;
 	struct group_desc *group;
 	const unsigned int *pins;
+	int ret;
 
 	func = pinmux_generic_get_function(pctldev, func_selector);
 	if (!func)
@@ -577,6 +595,10 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 		u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
 		u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
 
+		ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin);
+		if (ret)
+			return ret;
+
 		dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
 			RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
 
@@ -831,23 +853,6 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
 	return ret;
 }
 
-static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
-				   u64 cfg, u32 port, u8 bit)
-{
-	u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
-	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
-	u64 data;
-
-	if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
-		return -EINVAL;
-
-	data = pctrl->data->port_pin_configs[port];
-	if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
-		return -EINVAL;
-
-	return 0;
-}
-
 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
 				 u8 bit, u32 mask)
 {
@@ -1275,7 +1280,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
 	} else {
 		bit = RZG2L_PIN_ID_TO_PIN(_pin);
 
-		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+		if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
 			return -EINVAL;
 	}
 
@@ -1434,7 +1439,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
 	} else {
 		bit = RZG2L_PIN_ID_TO_PIN(_pin);
 
-		if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+		if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
 			return -EINVAL;
 	}
 
@@ -1672,7 +1677,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
 	u8 reg8;
 	int ret;
 
-	ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
+	ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit);
 	if (ret)
 		return ret;
 
-- 
2.43.0

[PATCH 6.12.y-cip 2/5] pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit 837afa592c6234be82acb5d23e0a39e9befdaa85 ]

Renesas RZ/G3E supports a power-saving mode where power to most of the
SoC components is lost, including the PIN controller.  Save and restore
the Schmitt control register contents to ensure the functionality is
preserved after a suspend/resume cycle.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250819084022.20512-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index a8887acfdef8..8b5a8f0b2c4d 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -321,6 +321,7 @@ struct rzg2l_pinctrl_pin_settings {
  * @iolh: IOLH registers cache
  * @pupd: PUPD registers cache
  * @ien: IEN registers cache
+ * @smt: SMT registers cache
  * @sd_ch: SD_CH registers cache
  * @eth_poc: ET_POC registers cache
  * @oen: Output Enable register cache
@@ -334,6 +335,7 @@ struct rzg2l_pinctrl_reg_cache {
 	u32	*iolh[2];
 	u32	*ien[2];
 	u32	*pupd[2];
+	u32	*smt;
 	u8	sd_ch[2];
 	u8	eth_poc[2];
 	u8	oen;
@@ -2702,6 +2704,10 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
 	if (!cache->pfc)
 		return -ENOMEM;
 
+	cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL);
+	if (!cache->smt)
+		return -ENOMEM;
+
 	for (u8 i = 0; i < 2; i++) {
 		u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
 
@@ -2963,7 +2969,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
 	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
 
 	for (u32 port = 0; port < nports; port++) {
-		bool has_iolh, has_ien, has_pupd;
+		bool has_iolh, has_ien, has_pupd, has_smt;
 		u32 off, caps;
 		u8 pincnt;
 		u64 cfg;
@@ -2976,6 +2982,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
 		has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
 		has_ien = !!(caps & PIN_CFG_IEN);
 		has_pupd = !!(caps & PIN_CFG_PUPD);
+		has_smt = !!(caps & PIN_CFG_SMT);
 
 		if (suspend)
 			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
@@ -3014,6 +3021,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
 							 cache->ien[1][port]);
 			}
 		}
+
+		if (has_smt)
+			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);
 	}
 }
 
-- 
2.43.0

[PATCH 6.12.y-cip 3/5] pinctrl: renesas: rzg2l: Drop unnecessary pin configurations

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit fb8a7900dcba3764902ff9f0b3824f8818b3f4df ]

There is no need to reconfigure a pin if the pin's configuration
values are the same as the reset values.  E.g. the PS0 pin configuration
for the NMI function is PMC = 1 and PFC = 0, which is the same as the
reset values.  Currently the code is first setting it to GPIO HI-Z state
and then again reconfiguring to the NMI function, leading to spurious
IRQs.  Fix this by dropping unnecessary pin configuration from the
driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250909104247.3309-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[ Biju: replaced raw_spin_unlock_irqrestore()->spin_unlock_irqrestore() as
there will be a stable fixes patch later to use raw_spin_*()]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 8b5a8f0b2c4d..d6f69532a0e7 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -541,9 +541,16 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 				       u8 pin, u8 off, u8 func)
 {
 	unsigned long flags;
-	u32 reg;
+	u32 reg, pfc;
 
+	/* Switching to GPIO is not required if reset value is same as func */
 	spin_lock_irqsave(&pctrl->lock, flags);
+	reg = readb(pctrl->base + PMC(off));
+	pfc = readl(pctrl->base + PFC(off));
+	if ((reg & BIT(pin)) && (((pfc >> (pin * 4)) & PFC_MASK) == func)) {
+		spin_unlock_irqrestore(&pctrl->lock, flags);
+		return;
+	}
 
 	/* Set pin to 'Non-use (Hi-Z input protection)'  */
 	reg = readw(pctrl->base + PM(off));
@@ -557,9 +564,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 	writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
 
 	/* Select Pin function mode with PFC register */
-	reg = readl(pctrl->base + PFC(off));
-	reg &= ~(PFC_MASK << (pin * 4));
-	writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
+	pfc &= ~(PFC_MASK << (pin * 4));
+	writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off));
 
 	/* Switch to Peripheral pin function with PMC register */
 	reg = readb(pctrl->base + PMC(off));
@@ -3111,11 +3117,18 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
 		pm = readw(pctrl->base + PM(off));
 		for_each_set_bit(pin, &pinmap, max_pin) {
 			struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+			u32 pfc_val, pfc_mask;
 
 			/* Nothing to do if PFC was not configured before. */
 			if (!(cache->pmc[port] & BIT(pin)))
 				continue;
 
+			pfc_val = readl(pctrl->base + PFC(off));
+			pfc_mask = PFC_MASK << (pin * 4);
+			/* Nothing to do if reset value of the pin is same as cached value */
+			if ((cache->pfc[port] & pfc_mask) == (pfc_val & pfc_mask))
+				continue;
+
 			/* Set pin to 'Non-use (Hi-Z input protection)' */
 			pm &= ~(PM_MASK << (pin * 2));
 			writew(pm, pctrl->base + PM(off));
@@ -3125,8 +3138,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
 			writeb(pmc, pctrl->base + PMC(off));
 
 			/* Select Pin function mode. */
-			pfc &= ~(PFC_MASK << (pin * 4));
-			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
+			pfc &= ~pfc_mask;
+			pfc |= (cache->pfc[port] & pfc_mask);
 			writel(pfc, pctrl->base + PFC(off));
 
 			/* Switch to Peripheral pin function. */
-- 
2.43.0

[PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]

RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
USER_SW3 and SLEEP button with NMI support. Add a DT node in device tree
to instantiate the gpio-keys driver for these buttons.

The system can enter into STR state by pressing the sleep button and
wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
configured as wakeup-source, so it can wakeup the system during s2idle.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250702092755.70847-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[Biju: Squashed the commit 3e5df910b592d4 ("arm64: dts: renesas:
r9a09g047e57-smarc: Fix gpio key's pin control node"]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 37 +++++++++++++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 31 ++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 2454a9743df2..9f6716fa1086 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /* Switch selection settings */
+#define SW_LCD_EN		0
 #define SW_GPIO8_CAN0_STB	0
 #define SW_GPIO9_CAN1_STB	0
 #define SW_LCD_EN		0
@@ -15,7 +16,16 @@
 #define SW_SD0_DEV_SEL		0
 #define SW_SDIO_M2E		0
 
+#define PMOD_GPIO4		0
+#define PMOD_GPIO6		0
+#define PMOD_GPIO7		0
+
+#define KEY_1_GPIO		RZG3E_GPIO(3, 1)
+#define KEY_2_GPIO		RZG3E_GPIO(8, 4)
+#define KEY_3_GPIO		RZG3E_GPIO(8, 5)
+
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
 #include "r9a09g047e57.dtsi"
 #include "rzg3e-smarc-som.dtsi"
@@ -79,6 +89,29 @@ &i2c0 {
 	pinctrl-names = "default";
 };
 
+&keys {
+	pinctrl-0 = <&nmi_pins>;
+	pinctrl-names = "default";
+
+	key-sleep {
+		interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
+		linux,code = <KEY_SLEEP>;
+		label = "SLEEP";
+		debounce-interval = <20>;
+	};
+#if PMOD_GPIO4
+	/delete-node/ key-1;
+#endif
+
+#if SW_LCD_EN || PMOD_GPIO6
+	/delete-node/ key-2;
+#endif
+
+#if SW_LCD_EN || PMOD_GPIO7
+	/delete-node/ key-3;
+#endif
+};
+
 &pinctrl {
 	canfd_pins: canfd {
 		can1_pins: can1 {
@@ -97,6 +130,10 @@ i2c0_pins: i2c0 {
 			 <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
 	};
 
+	nmi_pins: nmi {
+		pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 3cac292f20b3..58561da3007a 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -23,6 +23,9 @@
  * SW_GPIO9_CAN1_STB:
  *	0 - Connect to GPIO9 PMOD (default)
  *	1 - Connect to CAN1 transceiver STB pin
+ *
+ * GPIO keys are enabled by default. Use PMOD_GPIO macros to disable them
+ * if needed.
  */
 
 / {
@@ -53,6 +56,34 @@ can_transceiver1: can-phy1 {
 		max-bitrate = <8000000>;
 		status = "disabled";
 	};
+
+	keys: keys {
+		compatible = "gpio-keys";
+
+		key-1 {
+			interrupts-extended = <&pinctrl KEY_1_GPIO IRQ_TYPE_EDGE_FALLING>;
+			linux,code = <KEY_1>;
+			label = "USER_SW1";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-2 {
+			interrupts-extended = <&pinctrl KEY_2_GPIO IRQ_TYPE_EDGE_FALLING>;
+			linux,code = <KEY_2>;
+			label = "USER_SW2";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+
+		key-3 {
+			interrupts-extended = <&pinctrl KEY_3_GPIO IRQ_TYPE_EDGE_FALLING>;
+			linux,code = <KEY_3>;
+			label = "USER_SW3";
+			wakeup-source;
+			debounce-interval = <20>;
+		};
+	};
 };
 
 &canfd {
-- 
2.43.0

[PATCH 6.12.y-cip 5/5] arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI function

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

[ Upstream commit 4b9e0d8aa96c92be0073825344b661afc49242aa ]

The latest RZ/G3E pin control document (rev 1.2) recommends using
Schmitt input when PS0 pin used as NMI function.  Enable Schmitt input
for PS0 pin.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250817145135.166591-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 9f6716fa1086..08e814c03fa8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -132,6 +132,7 @@ i2c0_pins: i2c0 {
 
 	nmi_pins: nmi {
 		pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
+		input-schmitt-enable;
 	};
 
 	scif_pins: scif {
-- 
2.43.0

RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[nobuhiro.iwamatsu.x90]

Hi Biju,

Thank for your patch.

> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: Friday, December 19, 2025 9:29 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○Ｃ
> ＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc:
> Add gpio keys
> 
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> 
> RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
> USER_SW3 and SLEEP button with NMI support. Add a DT node in device tree
> to instantiate the gpio-keys driver for these buttons.
> 
> The system can enter into STR state by pressing the sleep button and wakeup
> from STR is done by pressing power button. The USER_SW{1,2,3} configured as
> wakeup-source, so it can wakeup the system during s2idle.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Link:
> https://lore.kernel.org/20250702092755.70847-1-biju.das.jz@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> [Biju: Squashed the commit 3e5df910b592d4 ("arm64: dts: renesas:
> r9a09g047e57-smarc: Fix gpio key's pin control node"]

Why did you need to squash the commit?

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 37
> +++++++++++++++++++
>  .../boot/dts/renesas/renesas-smarc2.dtsi      | 31
> ++++++++++++++++
>  2 files changed, 68 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> index 2454a9743df2..9f6716fa1086 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -8,6 +8,7 @@
>  /dts-v1/;
> 
>  /* Switch selection settings */
> +#define SW_LCD_EN		0
>  #define SW_GPIO8_CAN0_STB	0
>  #define SW_GPIO9_CAN1_STB	0
>  #define SW_LCD_EN		0
> @@ -15,7 +16,16 @@
>  #define SW_SD0_DEV_SEL		0
>  #define SW_SDIO_M2E		0
> 
> +#define PMOD_GPIO4		0
> +#define PMOD_GPIO6		0
> +#define PMOD_GPIO7		0
> +
> +#define KEY_1_GPIO		RZG3E_GPIO(3, 1)
> +#define KEY_2_GPIO		RZG3E_GPIO(8, 4)
> +#define KEY_3_GPIO		RZG3E_GPIO(8, 5)
> +
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
>  #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
>  #include "r9a09g047e57.dtsi"
>  #include "rzg3e-smarc-som.dtsi"
> @@ -79,6 +89,29 @@ &i2c0 {
>  	pinctrl-names = "default";
>  };
> 
> +&keys {
> +	pinctrl-0 = <&nmi_pins>;
> +	pinctrl-names = "default";
> +
> +	key-sleep {
> +		interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
> +		linux,code = <KEY_SLEEP>;
> +		label = "SLEEP";
> +		debounce-interval = <20>;
> +	};
> +#if PMOD_GPIO4
> +	/delete-node/ key-1;
> +#endif
> +
> +#if SW_LCD_EN || PMOD_GPIO6
> +	/delete-node/ key-2;
> +#endif
> +
> +#if SW_LCD_EN || PMOD_GPIO7
> +	/delete-node/ key-3;
> +#endif
> +};
> +
>  &pinctrl {
>  	canfd_pins: canfd {
>  		can1_pins: can1 {
> @@ -97,6 +130,10 @@ i2c0_pins: i2c0 {
>  			 <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
>  	};
> 
> +	nmi_pins: nmi {
> +		pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
> +	};
> +
>  	scif_pins: scif {
>  		pins = "SCIF_TXD", "SCIF_RXD";
>  		renesas,output-impedance = <1>;
> diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> index 3cac292f20b3..58561da3007a 100644
> --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> @@ -23,6 +23,9 @@
>   * SW_GPIO9_CAN1_STB:
>   *	0 - Connect to GPIO9 PMOD (default)
>   *	1 - Connect to CAN1 transceiver STB pin
> + *
> + * GPIO keys are enabled by default. Use PMOD_GPIO macros to disable
> + them
> + * if needed.
>   */
> 
>  / {
> @@ -53,6 +56,34 @@ can_transceiver1: can-phy1 {
>  		max-bitrate = <8000000>;
>  		status = "disabled";
>  	};
> +
> +	keys: keys {
> +		compatible = "gpio-keys";
> +
> +		key-1 {
> +			interrupts-extended = <&pinctrl KEY_1_GPIO
> IRQ_TYPE_EDGE_FALLING>;
> +			linux,code = <KEY_1>;
> +			label = "USER_SW1";
> +			wakeup-source;
> +			debounce-interval = <20>;
> +		};
> +
> +		key-2 {
> +			interrupts-extended = <&pinctrl KEY_2_GPIO
> IRQ_TYPE_EDGE_FALLING>;
> +			linux,code = <KEY_2>;
> +			label = "USER_SW2";
> +			wakeup-source;
> +			debounce-interval = <20>;
> +		};
> +
> +		key-3 {
> +			interrupts-extended = <&pinctrl KEY_3_GPIO
> IRQ_TYPE_EDGE_FALLING>;
> +			linux,code = <KEY_3>;
> +			label = "USER_SW3";
> +			wakeup-source;
> +			debounce-interval = <20>;
> +		};
> +	};
>  };
> 
>  &canfd {
> --
> 2.43.0

Best regards,
  Nobuhiro

RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[Biju Das]

Hi Nobuhiro-San,

> -----Original Message-----
> From: nobuhiro.iwamatsu.x90@mail.toshiba <nobuhiro.iwamatsu.x90@mail.toshiba>
> Sent: 24 December 2025 05:17
> Subject: RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
> 
> Hi Biju,
> 
> Thank for your patch.
> 
> > -----Original Message-----
> > From: Biju <biju.das.au@gmail.com>
> > Sent: Friday, December 19, 2025 9:29 PM
> > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○Ｃ
> > ＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek <pavel@denx.de>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc:
> > Add gpio keys
> >
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> >
> > RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
> > USER_SW3 and SLEEP button with NMI support. Add a DT node in device
> > tree to instantiate the gpio-keys driver for these buttons.
> >
> > The system can enter into STR state by pressing the sleep button and
> > wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
> > configured as wakeup-source, so it can wakeup the system during s2idle.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Link:
> > https://lore.kernel.org/20250702092755.70847-1-biju.das.jz@bp.renesas.
> > com
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > [Biju: Squashed the commit 3e5df910b592d4 ("arm64: dts: renesas:
> > r9a09g047e57-smarc: Fix gpio key's pin control node"]
> 
> Why did you need to squash the commit?

Previously Pavel mentioned to squash fixes patches like this
So that cip-kenel have clean functional patch.

Cheers,
Biju

> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 37
> > +++++++++++++++++++
> >  .../boot/dts/renesas/renesas-smarc2.dtsi      | 31
> > ++++++++++++++++
> >  2 files changed, 68 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > index 2454a9743df2..9f6716fa1086 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > @@ -8,6 +8,7 @@
> >  /dts-v1/;
> >
> >  /* Switch selection settings */
> > +#define SW_LCD_EN		0
> >  #define SW_GPIO8_CAN0_STB	0
> >  #define SW_GPIO9_CAN1_STB	0
> >  #define SW_LCD_EN		0
> > @@ -15,7 +16,16 @@
> >  #define SW_SD0_DEV_SEL		0
> >  #define SW_SDIO_M2E		0
> >
> > +#define PMOD_GPIO4		0
> > +#define PMOD_GPIO6		0
> > +#define PMOD_GPIO7		0
> > +
> > +#define KEY_1_GPIO		RZG3E_GPIO(3, 1)
> > +#define KEY_2_GPIO		RZG3E_GPIO(8, 4)
> > +#define KEY_3_GPIO		RZG3E_GPIO(8, 5)
> > +
> >  #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> >  #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
> >  #include "r9a09g047e57.dtsi"
> >  #include "rzg3e-smarc-som.dtsi"
> > @@ -79,6 +89,29 @@ &i2c0 {
> >  	pinctrl-names = "default";
> >  };
> >
> > +&keys {
> > +	pinctrl-0 = <&nmi_pins>;
> > +	pinctrl-names = "default";
> > +
> > +	key-sleep {
> > +		interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
> > +		linux,code = <KEY_SLEEP>;
> > +		label = "SLEEP";
> > +		debounce-interval = <20>;
> > +	};
> > +#if PMOD_GPIO4
> > +	/delete-node/ key-1;
> > +#endif
> > +
> > +#if SW_LCD_EN || PMOD_GPIO6
> > +	/delete-node/ key-2;
> > +#endif
> > +
> > +#if SW_LCD_EN || PMOD_GPIO7
> > +	/delete-node/ key-3;
> > +#endif
> > +};
> > +
> >  &pinctrl {
> >  	canfd_pins: canfd {
> >  		can1_pins: can1 {
> > @@ -97,6 +130,10 @@ i2c0_pins: i2c0 {
> >  			 <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
> >  	};
> >
> > +	nmi_pins: nmi {
> > +		pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
> > +	};
> > +
> >  	scif_pins: scif {
> >  		pins = "SCIF_TXD", "SCIF_RXD";
> >  		renesas,output-impedance = <1>;
> > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > index 3cac292f20b3..58561da3007a 100644
> > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > @@ -23,6 +23,9 @@
> >   * SW_GPIO9_CAN1_STB:
> >   *	0 - Connect to GPIO9 PMOD (default)
> >   *	1 - Connect to CAN1 transceiver STB pin
> > + *
> > + * GPIO keys are enabled by default. Use PMOD_GPIO macros to disable
> > + them
> > + * if needed.
> >   */
> >
> >  / {
> > @@ -53,6 +56,34 @@ can_transceiver1: can-phy1 {
> >  		max-bitrate = <8000000>;
> >  		status = "disabled";
> >  	};
> > +
> > +	keys: keys {
> > +		compatible = "gpio-keys";
> > +
> > +		key-1 {
> > +			interrupts-extended = <&pinctrl KEY_1_GPIO
> > IRQ_TYPE_EDGE_FALLING>;
> > +			linux,code = <KEY_1>;
> > +			label = "USER_SW1";
> > +			wakeup-source;
> > +			debounce-interval = <20>;
> > +		};
> > +
> > +		key-2 {
> > +			interrupts-extended = <&pinctrl KEY_2_GPIO
> > IRQ_TYPE_EDGE_FALLING>;
> > +			linux,code = <KEY_2>;
> > +			label = "USER_SW2";
> > +			wakeup-source;
> > +			debounce-interval = <20>;
> > +		};
> > +
> > +		key-3 {
> > +			interrupts-extended = <&pinctrl KEY_3_GPIO
> > IRQ_TYPE_EDGE_FALLING>;
> > +			linux,code = <KEY_3>;
> > +			label = "USER_SW3";
> > +			wakeup-source;
> > +			debounce-interval = <20>;
> > +		};
> > +	};
> >  };
> >
> >  &canfd {
> > --
> > 2.43.0
> 
> Best regards,
>   Nobuhiro

RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[nobuhiro.iwamatsu.x90]

Hi Biju,

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Wednesday, December 24, 2025 6:30 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro.iwamatsu.x90@mail.toshiba>; biju.das.au <biju.das.au@gmail.com>;
> cip-dev@lists.cip-project.org; pavel@denx.de
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc:
> Add gpio keys
> 
> Hi Nobuhiro-San,
> 
> > -----Original Message-----
> > From: nobuhiro.iwamatsu.x90@mail.toshiba
> > <nobuhiro.iwamatsu.x90@mail.toshiba>
> > Sent: 24 December 2025 05:17
> > Subject: RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas:
> > r9a09g047e57-smarc: Add gpio keys
> >
> > Hi Biju,
> >
> > Thank for your patch.
> >
> > > -----Original Message-----
> > > From: Biju <biju.das.au@gmail.com>
> > > Sent: Friday, December 19, 2025 9:29 PM
> > > To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> Ｃ
> > > ＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek
> > > <pavel@denx.de>
> > > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Subject: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas:
> r9a09g047e57-smarc:
> > > Add gpio keys
> > >
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> > >
> > > RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2
> and
> > > USER_SW3 and SLEEP button with NMI support. Add a DT node in device
> > > tree to instantiate the gpio-keys driver for these buttons.
> > >
> > > The system can enter into STR state by pressing the sleep button and
> > > wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
> > > configured as wakeup-source, so it can wakeup the system during s2idle.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Link:
> > > https://lore.kernel.org/20250702092755.70847-1-biju.das.jz@bp.renesas.
> > > com
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > [Biju: Squashed the commit 3e5df910b592d4 ("arm64: dts: renesas:
> > > r9a09g047e57-smarc: Fix gpio key's pin control node"]
> >
> > Why did you need to squash the commit?
> 
> Previously Pavel mentioned to squash fixes patches like this So that cip-kenel
> have clean functional patch.

I see. Thank you for letting me know.

> 
> Cheers,
> Biju
> 

Best regards,
  Nobuhiro

> >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 37
> > > +++++++++++++++++++
> > >  .../boot/dts/renesas/renesas-smarc2.dtsi      | 31
> > > ++++++++++++++++
> > >  2 files changed, 68 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > > b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > > index 2454a9743df2..9f6716fa1086 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > > @@ -8,6 +8,7 @@
> > >  /dts-v1/;
> > >
> > >  /* Switch selection settings */
> > > +#define SW_LCD_EN		0
> > >  #define SW_GPIO8_CAN0_STB	0
> > >  #define SW_GPIO9_CAN1_STB	0
> > >  #define SW_LCD_EN		0
> > > @@ -15,7 +16,16 @@
> > >  #define SW_SD0_DEV_SEL		0
> > >  #define SW_SDIO_M2E		0
> > >
> > > +#define PMOD_GPIO4		0
> > > +#define PMOD_GPIO6		0
> > > +#define PMOD_GPIO7		0
> > > +
> > > +#define KEY_1_GPIO		RZG3E_GPIO(3, 1)
> > > +#define KEY_2_GPIO		RZG3E_GPIO(8, 4)
> > > +#define KEY_3_GPIO		RZG3E_GPIO(8, 5)
> > > +
> > >  #include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/input/input.h>
> > >  #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
> > >  #include "r9a09g047e57.dtsi"
> > >  #include "rzg3e-smarc-som.dtsi"
> > > @@ -79,6 +89,29 @@ &i2c0 {
> > >  	pinctrl-names = "default";
> > >  };
> > >
> > > +&keys {
> > > +	pinctrl-0 = <&nmi_pins>;
> > > +	pinctrl-names = "default";
> > > +
> > > +	key-sleep {
> > > +		interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>;
> > > +		linux,code = <KEY_SLEEP>;
> > > +		label = "SLEEP";
> > > +		debounce-interval = <20>;
> > > +	};
> > > +#if PMOD_GPIO4
> > > +	/delete-node/ key-1;
> > > +#endif
> > > +
> > > +#if SW_LCD_EN || PMOD_GPIO6
> > > +	/delete-node/ key-2;
> > > +#endif
> > > +
> > > +#if SW_LCD_EN || PMOD_GPIO7
> > > +	/delete-node/ key-3;
> > > +#endif
> > > +};
> > > +
> > >  &pinctrl {
> > >  	canfd_pins: canfd {
> > >  		can1_pins: can1 {
> > > @@ -97,6 +130,10 @@ i2c0_pins: i2c0 {
> > >  			 <RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
> > >  	};
> > >
> > > +	nmi_pins: nmi {
> > > +		pinmux = <RZG3E_PORT_PINMUX(S, 0, 0)>; /* NMI */
> > > +	};
> > > +
> > >  	scif_pins: scif {
> > >  		pins = "SCIF_TXD", "SCIF_RXD";
> > >  		renesas,output-impedance = <1>;
> > > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > index 3cac292f20b3..58561da3007a 100644
> > > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > > @@ -23,6 +23,9 @@
> > >   * SW_GPIO9_CAN1_STB:
> > >   *	0 - Connect to GPIO9 PMOD (default)
> > >   *	1 - Connect to CAN1 transceiver STB pin
> > > + *
> > > + * GPIO keys are enabled by default. Use PMOD_GPIO macros to
> > > + disable them
> > > + * if needed.
> > >   */
> > >
> > >  / {
> > > @@ -53,6 +56,34 @@ can_transceiver1: can-phy1 {
> > >  		max-bitrate = <8000000>;
> > >  		status = "disabled";
> > >  	};
> > > +
> > > +	keys: keys {
> > > +		compatible = "gpio-keys";
> > > +
> > > +		key-1 {
> > > +			interrupts-extended = <&pinctrl KEY_1_GPIO
> > > IRQ_TYPE_EDGE_FALLING>;
> > > +			linux,code = <KEY_1>;
> > > +			label = "USER_SW1";
> > > +			wakeup-source;
> > > +			debounce-interval = <20>;
> > > +		};
> > > +
> > > +		key-2 {
> > > +			interrupts-extended = <&pinctrl KEY_2_GPIO
> > > IRQ_TYPE_EDGE_FALLING>;
> > > +			linux,code = <KEY_2>;
> > > +			label = "USER_SW2";
> > > +			wakeup-source;
> > > +			debounce-interval = <20>;
> > > +		};
> > > +
> > > +		key-3 {
> > > +			interrupts-extended = <&pinctrl KEY_3_GPIO
> > > IRQ_TYPE_EDGE_FALLING>;
> > > +			linux,code = <KEY_3>;
> > > +			label = "USER_SW3";
> > > +			wakeup-source;
> > > +			debounce-interval = <20>;
> > > +		};
> > > +	};
> > >  };
> > >
> > >  &canfd {
> > > --
> > > 2.43.0
> >
> > Best regards,
> >   Nobuhiro

Re: [cip-dev] [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1452 bytes --]

Hi!

> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> > >
> > > RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
> > > USER_SW3 and SLEEP button with NMI support. Add a DT node in device
> > > tree to instantiate the gpio-keys driver for these buttons.
> > >
> > > The system can enter into STR state by pressing the sleep button and
> > > wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
> > > configured as wakeup-source, so it can wakeup the system during s2idle.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Link:
> > > https://lore.kernel.org/20250702092755.70847-1-biju.das.jz@bp.renesas.
> > > com
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > [Biju: Squashed the commit 3e5df910b592d4 ("arm64: dts: renesas:
> > > r9a09g047e57-smarc: Fix gpio key's pin control node"]
> > 
> > Why did you need to squash the commit?
> 
> Previously Pavel mentioned to squash fixes patches like this
> So that cip-kenel have clean functional patch.

I'm not sure if I would request the squash here; I guess both options
would be okay here.

Best regards,
								Pavel

-- 
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

Re: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1594 bytes --]

Hi!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> 
> RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
> USER_SW3 and SLEEP button with NMI support. Add a DT node in device tree
> to instantiate the gpio-keys driver for these buttons.
> 
> The system can enter into STR state by pressing the sleep button and
> wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
> configured as wakeup-source, so it can wakeup the system during
> s2idle.


> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -8,6 +8,7 @@
>  /dts-v1/;
>  
>  /* Switch selection settings */
> +#define SW_LCD_EN		0
>  #define SW_GPIO8_CAN0_STB	0
>  #define SW_GPIO9_CAN1_STB	0
>  #define SW_LCD_EN		0

SW_LCD_EN already exists, 3 lines below. This may confuse someone when
the defines get out of sync.

> +	keys: keys {
> +		compatible = "gpio-keys";
> +
> +		key-1 {
> +			interrupts-extended = <&pinctrl KEY_1_GPIO IRQ_TYPE_EDGE_FALLING>;
> +			linux,code = <KEY_1>;
> +			label = "USER_SW1";
> +			wakeup-source;
> +			debounce-interval = <20>;
> +		};

Are they buttons (they return to 0 when force is released) or switches
(you move them to 1 position, then you have to move them again into 0
position)?

If they are buttons, label is quite confusing. If they are switches,
more fixing may be needed.

Best regards,
								Pavel
-- 
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

Re: [PATCH 6.12.y-cip 0/5] Add gpio keys/sleep button support for RZ/G3E

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 714 bytes --]

Hi!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add gpio keys support for waking up from s2idle and sleep button support
> for entering to STR. Wakeup of STR is by pressing and holding power
> button. All the patches in this series are cherry-picked from
> mainline.

Series looks okay to me. I had some minor comments here, but those
should be fixed in mainline, first, so they should not block the
merge.

Reviewed-by: Pavel Machek <pavel@denx.de>

I can apply the series if it passes testing and there are no other
comments.

Best regards,
								Pavel
-- 
In cooperation with DENX Software Engineering GmbH, HRB 165235 Munich,
Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

RE: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys

[Biju Das]

Hi Pavel,

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 29 December 2025 21:12
> Subject: Re: [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
> 
> Hi!
> 
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > [ Upstram commit 9e95446b0cf93a91bc3b3b64c6d423f4024a6ff0 ]
> >
> > RZ/G3E SMARC EVK  has 3 user buttons called USER_SW1, USER_SW2 and
> > USER_SW3 and SLEEP button with NMI support. Add a DT node in device
> > tree to instantiate the gpio-keys driver for these buttons.
> >
> > The system can enter into STR state by pressing the sleep button and
> > wakeup from STR is done by pressing power button. The USER_SW{1,2,3}
> > configured as wakeup-source, so it can wakeup the system during
> > s2idle.
> 
> 
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > @@ -8,6 +8,7 @@
> >  /dts-v1/;
> >
> >  /* Switch selection settings */
> > +#define SW_LCD_EN		0
> >  #define SW_GPIO8_CAN0_STB	0
> >  #define SW_GPIO9_CAN1_STB	0
> >  #define SW_LCD_EN		0
> 
> SW_LCD_EN already exists, 3 lines below. This may confuse someone when the defines get out of sync.


OK. I will backport the patch [1] separately

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/commit/?h=next&id=fdf74a6cb506ed4f516c34b594d56dd1358bcc1c


> 
> > +	keys: keys {
> > +		compatible = "gpio-keys";
> > +
> > +		key-1 {
> > +			interrupts-extended = <&pinctrl KEY_1_GPIO IRQ_TYPE_EDGE_FALLING>;
> > +			linux,code = <KEY_1>;
> > +			label = "USER_SW1";
> > +			wakeup-source;
> > +			debounce-interval = <20>;
> > +		};
> 
> Are they buttons (they return to 0 when force is released) or switches (you move them to 1 position,
> then you have to move them again into 0 position)?
> 
> If they are buttons, label is quite confusing. If they are switches, more fixing may be needed.

It is buttons. But on the board. it is labelled as "USER_SW1".

Cheers,
Biju