* [PATCH 6.12.y-cip 1/4] clk: renesas: r9a09g047: Add DMAC clocks and resets
2026-01-28 16:00 [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Tommaso Merciai
@ 2026-01-28 16:00 ` Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 2/4] dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs Tommaso Merciai
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Tommaso Merciai @ 2026-01-28 16:00 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
commit 059db30b32e968fdbf6e416411fb78d481ff94bd upstream.
Add clock and reset entries for the Renesas RZ/G3E DMAC IPs.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250801084825.471011-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 26e2be7667eb..4e8881e0006b 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -48,6 +48,8 @@ enum clk_ids {
CLK_PLLDTY_ACPU_DIV2,
CLK_PLLDTY_ACPU_DIV4,
CLK_PLLDTY_DIV8,
+ CLK_PLLDTY_RCPU,
+ CLK_PLLDTY_RCPU_DIV4,
CLK_PLLETH_DIV_250_FIX,
CLK_PLLETH_DIV_125_FIX,
CLK_CSDIV_PLLETH_GBE0,
@@ -157,6 +159,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
+ DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
+ DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
@@ -180,6 +184,16 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
+ DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
+ BUS_MSTOP(5, BIT(9))),
+ DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
+ BUS_MSTOP(3, BIT(2))),
+ DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
+ BUS_MSTOP(3, BIT(3))),
+ DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
+ BUS_MSTOP(10, BIT(11))),
+ DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
+ BUS_MSTOP(10, BIT(12))),
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
BUS_MSTOP_NONE),
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
@@ -300,6 +314,11 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
+ DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
+ DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
+ DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
+ DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
+ DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6.12.y-cip 2/4] dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs
2026-01-28 16:00 [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 1/4] clk: renesas: r9a09g047: Add DMAC clocks and resets Tommaso Merciai
@ 2026-01-28 16:00 ` Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 3/4] arm64: dts: renesas: r9a09g047: Add DMAC nodes Tommaso Merciai
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Tommaso Merciai @ 2026-01-28 16:00 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
commit cc0bacac6de7763a038550cf43cb94634d8be9cd upstream.
The DMAC block on the RZ/G3E SoC is identical to the one found on the
RZ/V2H(P) SoC.
No driver changes are required, as `renesas,r9a09g057-dmac` will be used
as a fallback compatible string on the RZ/G3E SoC.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250801084825.471011-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 52c247dc5fde..a43b6f29a688 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -20,6 +20,11 @@ properties:
- renesas,r9a08g045-dmac # RZ/G3S
- const: renesas,rz-dmac
+ - items:
+ - enum:
+ - renesas,r9a09g047-dmac # RZ/G3E
+ - const: renesas,r9a09g057-dmac
+
- const: renesas,r9a09g057-dmac # RZ/V2H(P)
reg:
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6.12.y-cip 3/4] arm64: dts: renesas: r9a09g047: Add DMAC nodes
2026-01-28 16:00 [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 1/4] clk: renesas: r9a09g047: Add DMAC clocks and resets Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 2/4] dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs Tommaso Merciai
@ 2026-01-28 16:00 ` Tommaso Merciai
2026-01-28 16:00 ` [PATCH 6.12.y-cip 4/4] arm64: dts: renesas: r9a09g047: Move interrupt-parent to root node Tommaso Merciai
2026-01-28 19:36 ` [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Pavel Machek
4 siblings, 0 replies; 7+ messages in thread
From: Tommaso Merciai @ 2026-01-28 16:00 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
commit c44c51bc3566412075c66e0064e17c0c9cb5a638 upstream.
Add nodes for the DMAC IPs found on the Renesas RZ/G3E SoC.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250801084825.471011-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 170 +++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 42bf6a57df97..47d843c79021 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -301,6 +301,176 @@ xspi: spi@11030000 {
status = "disabled";
};
+ dmac0: dma-controller@11400000 {
+ compatible = "renesas,r9a09g047-dmac",
+ "renesas,r9a09g057-dmac";
+ reg = <0 0x11400000 0 0x10000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x0>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x31>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 4>;
+ };
+
+ dmac1: dma-controller@14830000 {
+ compatible = "renesas,r9a09g047-dmac",
+ "renesas,r9a09g057-dmac";
+ reg = <0 0x14830000 0 0x10000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x1>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x32>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac2: dma-controller@14840000 {
+ compatible = "renesas,r9a09g047-dmac",
+ "renesas,r9a09g057-dmac";
+ reg = <0 0x14840000 0 0x10000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x2>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x33>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac3: dma-controller@12000000 {
+ compatible = "renesas,r9a09g047-dmac",
+ "renesas,r9a09g057-dmac";
+ reg = <0 0x12000000 0 0x10000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x3>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x34>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
+ dmac4: dma-controller@12010000 {
+ compatible = "renesas,r9a09g047-dmac",
+ "renesas,r9a09g057-dmac";
+ reg = <0 0x12010000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x4>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x35>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 3>;
+ };
+
scif0: serial@11c01400 {
compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
reg = <0 0x11c01400 0 0x400>;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 6.12.y-cip 4/4] arm64: dts: renesas: r9a09g047: Move interrupt-parent to root node
2026-01-28 16:00 [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Tommaso Merciai
` (2 preceding siblings ...)
2026-01-28 16:00 ` [PATCH 6.12.y-cip 3/4] arm64: dts: renesas: r9a09g047: Add DMAC nodes Tommaso Merciai
@ 2026-01-28 16:00 ` Tommaso Merciai
2026-01-28 19:36 ` [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Pavel Machek
4 siblings, 0 replies; 7+ messages in thread
From: Tommaso Merciai @ 2026-01-28 16:00 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek
Cc: Biju Das, Lad Prabhakar, tomm.merciai
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
commit e57389d5547ee24b472ac5c8f8a7dc21b063ad73 upstream.
Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/87h5ws8o8g.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 47d843c79021..c8cbe53ad4b0 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -12,6 +12,7 @@ / {
compatible = "renesas,r9a09g047";
#address-cells = <2>;
#size-cells = <2>;
+ interrupt-parent = <&gic>;
audio_extal_clk: audio-clk {
compatible = "fixed-clock";
@@ -155,7 +156,6 @@ rtxin_clk: rtxin-clk {
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -1175,11 +1175,11 @@ stmmac_axi_setup: stmmac-axi-config {
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support
2026-01-28 16:00 [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Tommaso Merciai
` (3 preceding siblings ...)
2026-01-28 16:00 ` [PATCH 6.12.y-cip 4/4] arm64: dts: renesas: r9a09g047: Move interrupt-parent to root node Tommaso Merciai
@ 2026-01-28 19:36 ` Pavel Machek
2026-02-02 2:09 ` nobuhiro.iwamatsu.x90
4 siblings, 1 reply; 7+ messages in thread
From: Pavel Machek @ 2026-01-28 19:36 UTC (permalink / raw)
To: tommaso.merciai.xr
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar,
tomm.merciai
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Hi!
> This series adds DMAC support for the Renesas RZ/G3E SoC into linux-cip
> 6.12.y-cip kernel. Backported also commit
> e57389d5547ee24b472ac5c8f8a7dc21b063ad73 upstream on top of this series.
As with 6.1 version, this looks okay to me.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
I can apply the series if it passes testing and there are no other
comments.
Best regards,
Pavel
--
In cooperation with Nabla.
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^ permalink raw reply [flat|nested] 7+ messages in thread* RE: [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support
2026-01-28 19:36 ` [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support Pavel Machek
@ 2026-02-02 2:09 ` nobuhiro.iwamatsu.x90
0 siblings, 0 replies; 7+ messages in thread
From: nobuhiro.iwamatsu.x90 @ 2026-02-02 2:09 UTC (permalink / raw)
To: pavel, tommaso.merciai.xr
Cc: cip-dev, biju.das.jz, prabhakar.mahadev-lad.rj, tomm.merciai
Hi,
> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
> Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Thursday, January 29, 2026 4:36 AM
> To: tommaso.merciai.xr@bp.renesas.com
> Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek
> <pavel@nabladev.com>; Biju Das <biju.das.jz@bp.renesas.com>; Lad
> Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> tomm.merciai@gmail.com
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 0/4] Add RZ/G3E DMAC support
>
> Hi!
>
> > This series adds DMAC support for the Renesas RZ/G3E SoC into
> > linux-cip 6.12.y-cip kernel. Backported also commit
> > e57389d5547ee24b472ac5c8f8a7dc21b063ad73 upstream on top of this
> series.
>
> As with 6.1 version, this looks okay to me.
>
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
>
> I can apply the series if it passes testing and there are no other comments.
I reviewed this series and 6.1.y, looks good to me too.
I applied with Pavel's Reviewed-by tag and pushed, thanks!
>
> Best regards,
> Pavel
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 7+ messages in thread