From: Pavel Machek <pavel@nabladev.com>
To: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Cc: cip-dev@lists.cip-project.org, pavel@nabladev.com,
nobuhiro.iwamatsu.x90@mail.toshiba
Subject: Re: [PATCH 6.1.y-cip 03/11] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config
Date: Mon, 2 Feb 2026 14:19:22 +0100 [thread overview]
Message-ID: <aYCkWsWv+5CoAFFH@duo.ucw.cz> (raw)
In-Reply-To: <20260128132522.6902-4-ovidiu.panait.rb@renesas.com>
[-- Attachment #1: Type: text/plain, Size: 2098 bytes --]
Hi!
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> commit c432180a7d95081353a96fd6d5bd75b0fc8a27c3 upstream.
>
> Not all system controller registers are accessible from Linux. Accessing
> such registers generates synchronous external abort. Populate the
> readable_reg and writeable_reg members of the regmap config to inform the
> regmap core which registers can be accessed. The list will need to be
> updated whenever new system controller functionality is exported through
> regmap.
Ok.
> @@ -18,7 +37,57 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
> .specific_id_mask = GENMASK(27, 0),
> };
>
> +static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case SYS_XSPI_MAP_STAADD_CS0:
> + case SYS_XSPI_MAP_ENDADD_CS0:
> + case SYS_XSPI_MAP_STAADD_CS1:
> + case SYS_XSPI_MAP_ENDADD_CS1:
> + case SYS_GETH0_CFG:
> + case SYS_GETH1_CFG:
> + case SYS_PCIE_CFG:
> + case SYS_PCIE_MON:
> + case SYS_PCIE_ERR_MON:
> + case SYS_PCIE_PHY:
> + case SYS_I2C0_CFG:
> + case SYS_I2C1_CFG:
> + case SYS_I2C2_CFG:
> + case SYS_I2C3_CFG:
> + case SYS_I3C_CFG:
> + case SYS_USB_PWRRDY:
> + case SYS_PCIE_RST_RSM_B:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case SYS_XSPI_MAP_STAADD_CS0:
> + case SYS_XSPI_MAP_ENDADD_CS0:
> + case SYS_XSPI_MAP_STAADD_CS1:
> + case SYS_XSPI_MAP_ENDADD_CS1:
> + case SYS_PCIE_CFG:
> + case SYS_PCIE_PHY:
> + case SYS_I2C0_CFG:
> + case SYS_I2C1_CFG:
> + case SYS_I2C2_CFG:
> + case SYS_I2C3_CFG:
> + case SYS_I3C_CFG:
> + case SYS_USB_PWRRDY:
> + case SYS_PCIE_RST_RSM_B:
> + return true;
> + default:
> + return false;
> + }
> +}
But when register is writable, it will also always be readable, right?
So Imo readable should just do if (writable) return true, to reduce
code duplication.
Thanks and best regards,
Pavel
--
In cooperation with Nabla.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
next prev parent reply other threads:[~2026-02-02 13:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 13:25 [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 01/11] soc: renesas: rz-sysc: Add syscon/regmap support Ovidiu Panait
2026-02-02 13:17 ` [cip-dev] " Pavel Machek
2026-01-28 13:25 ` [PATCH 6.1.y-cip 02/11] soc: renesas: r9a09g056-sys: Populate max_register Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 03/11] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config Ovidiu Panait
2026-02-02 13:19 ` Pavel Machek [this message]
2026-01-28 13:25 ` [PATCH 6.1.y-cip 04/11] PM: domains: Add RZ/V2H compatible to PM domain detach list Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 05/11] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 06/11] thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC Ovidiu Panait
2026-02-02 13:21 ` Pavel Machek
2026-01-28 13:25 ` [PATCH 6.1.y-cip 07/11] thermal/drivers/renesas/rzg3e: Fix add " Ovidiu Panait
2026-02-02 13:29 ` Pavel Machek
2026-01-28 13:25 ` [PATCH 6.1.y-cip 08/11] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 09/11] clk: renesas: r9a09g057: Add clock and reset entries for TSU Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 10/11] arm64: dts: renesas: r9a09g057: Move interrupt-parent to root node Ovidiu Panait
2026-01-28 13:25 ` [PATCH 6.1.y-cip 11/11] arm64: dts: renesas: r9a09g057: Add TSU nodes Ovidiu Panait
2026-01-29 8:10 ` [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support nobuhiro.iwamatsu.x90
2026-02-02 2:00 ` nobuhiro.iwamatsu.x90
2026-02-02 13:48 ` [cip-dev] " Pavel Machek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aYCkWsWv+5CoAFFH@duo.ucw.cz \
--to=pavel@nabladev.com \
--cc=cip-dev@lists.cip-project.org \
--cc=nobuhiro.iwamatsu.x90@mail.toshiba \
--cc=ovidiu.panait.rb@renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox