[PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support

[PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support

[Ovidiu Panait]

Hi,

This series adds TSU support for the Renesas RZ/V2H SoC.

All patches, except for patch 4/11, were cherry-picked from mainline kernel.

Patch 4/11 is needed to fix asynchronous aborts during unbind. See the MSTOP
series [1] for more details.

[1] https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.beznea.uj@bp.renesas.com/

Best regards,
Ovidiu

Claudiu Beznea (2):
  soc: renesas: r9a09g056-sys: Populate max_register
  soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap
    config

John Madieu (5):
  soc: renesas: rz-sysc: Add syscon/regmap support
  dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
  thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas
    RZ/G3E SoC
  thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas
    RZ/G3E SoC
  arm64: defconfig: Enable the Renesas RZ/G3E thermal driver

Kuninori Morimoto (1):
  arm64: dts: renesas: r9a09g057: Move interrupt-parent to root node

Ovidiu Panait (3):
  PM: domains: Add RZ/V2H compatible to PM domain detach list
  clk: renesas: r9a09g057: Add clock and reset entries for TSU
  arm64: dts: renesas: r9a09g057: Add TSU nodes

 .../thermal/renesas,r9a09g047-tsu.yaml        |  87 +++
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  89 ++-
 arch/arm64/configs/defconfig                  |   1 +
 drivers/base/power/common.c                   |   1 +
 drivers/clk/renesas/r9a09g057-cpg.c           |   6 +
 drivers/soc/renesas/Kconfig                   |   1 +
 drivers/soc/renesas/r9a08g045-sysc.c          |  70 +++
 drivers/soc/renesas/r9a09g047-sys.c           |  80 +++
 drivers/soc/renesas/r9a09g056-sys.c           |  69 +++
 drivers/soc/renesas/r9a09g057-sys.c           | 102 ++++
 drivers/soc/renesas/rz-sysc.c                 |  32 +-
 drivers/soc/renesas/rz-sysc.h                 |   6 +
 drivers/thermal/Kconfig                       |   7 +
 drivers/thermal/Makefile                      |   1 +
 drivers/thermal/rzg3e_thermal.c               | 572 ++++++++++++++++++
 16 files changed, 1123 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
 create mode 100644 drivers/thermal/rzg3e_thermal.c

-- 
2.51.0

[PATCH 6.1.y-cip 01/11] soc: renesas: rz-sysc: Add syscon/regmap support

[Ovidiu Panait]

From: John Madieu <john.madieu.xa@bp.renesas.com>

commit 2da2740fb9c8e26b6b5e20d74f2ed1d49824236d upstream.

The RZ/G3E system controller has various registers that control or report
some properties specific to individual IPs. The regmap is registered as a
syscon device to allow these IP drivers to access the registers through the
regmap API.

As other RZ SoCs might have custom read/write callbacks or max-offsets,
register a custom regmap configuration.

[claudiu.beznea:
 - do not check the match->data validity in rz_sysc_probe() as it is
   always valid
 - dinamically allocate regmap_cfg]

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250818162859.9661-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/soc/renesas/Kconfig          |  1 +
 drivers/soc/renesas/r9a08g045-sysc.c |  1 +
 drivers/soc/renesas/r9a09g047-sys.c  |  1 +
 drivers/soc/renesas/r9a09g057-sys.c  |  1 +
 drivers/soc/renesas/rz-sysc.c        | 30 +++++++++++++++++++++++++++-
 drivers/soc/renesas/rz-sysc.h        |  2 ++
 6 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 121f0c928542..ee2c2222f1c4 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -488,6 +488,7 @@ config SYSC_R8A774B1
 
 config SYSC_RZ
 	bool "System controller for RZ SoCs" if COMPILE_TEST
+	select MFD_SYSCON
 
 config SYSC_R9A08G045
 	bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c
index f4db1431e036..0504d4e68761 100644
--- a/drivers/soc/renesas/r9a08g045-sysc.c
+++ b/drivers/soc/renesas/r9a08g045-sysc.c
@@ -20,4 +20,5 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
 
 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
 	.soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
+	.max_register = 0xe20,
 };
diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c
index cd2eb7782cfe..2e8426c03050 100644
--- a/drivers/soc/renesas/r9a09g047-sys.c
+++ b/drivers/soc/renesas/r9a09g047-sys.c
@@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco
 
 const struct rz_sysc_init_data rzg3e_sys_init_data = {
 	.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
+	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c
index 4c21cc29edbc..e3390e7c7fe5 100644
--- a/drivers/soc/renesas/r9a09g057-sys.c
+++ b/drivers/soc/renesas/r9a09g057-sys.c
@@ -64,4 +64,5 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initco
 
 const struct rz_sysc_init_data rzv2h_sys_init_data = {
 	.soc_id_init_data = &rzv2h_sys_soc_id_init_data,
+	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index ffa65fb4dade..9f79e299e6f4 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -5,9 +5,13 @@
  * Copyright (C) 2024 Renesas Electronics Corp.
  */
 
+#include <linux/cleanup.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
 #include <linux/sys_soc.h>
 
 #include "rz-sysc.h"
@@ -100,14 +104,23 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match);
 
 static int rz_sysc_probe(struct platform_device *pdev)
 {
+	const struct rz_sysc_init_data *data;
 	const struct of_device_id *match;
 	struct device *dev = &pdev->dev;
+	struct regmap *regmap;
 	struct rz_sysc *sysc;
+	int ret;
+
+	struct regmap_config *regmap_cfg __free(kfree) = kzalloc(sizeof(*regmap_cfg), GFP_KERNEL);
+	if (!regmap_cfg)
+		return -ENOMEM;
 
 	match = of_match_node(rz_sysc_match, dev->of_node);
 	if (!match)
 		return -ENODEV;
 
+	data = match->data;
+
 	sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL);
 	if (!sysc)
 		return -ENOMEM;
@@ -117,7 +130,22 @@ static int rz_sysc_probe(struct platform_device *pdev)
 		return PTR_ERR(sysc->base);
 
 	sysc->dev = dev;
-	return rz_sysc_soc_init(sysc, match);
+	ret = rz_sysc_soc_init(sysc, match);
+	if (ret)
+		return ret;
+
+	regmap_cfg->name = "rz_sysc_regs";
+	regmap_cfg->reg_bits = 32;
+	regmap_cfg->reg_stride = 4;
+	regmap_cfg->val_bits = 32;
+	regmap_cfg->fast_io = true;
+	regmap_cfg->max_register = data->max_register;
+
+	regmap = devm_regmap_init_mmio(dev, sysc->base, regmap_cfg);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	return of_syscon_register_regmap(dev->of_node, regmap);
 }
 
 static struct platform_driver rz_sysc_driver = {
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index 56bc047a1bff..8eec355d5d56 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -34,9 +34,11 @@ struct rz_sysc_soc_id_init_data {
 /**
  * struct rz_sysc_init_data - RZ SYSC initialization data
  * @soc_id_init_data: RZ SYSC SoC ID initialization data
+ * @max_register: Maximum SYSC register offset to be used by the regmap config
  */
 struct rz_sysc_init_data {
 	const struct rz_sysc_soc_id_init_data *soc_id_init_data;
+	u32 max_register;
 };
 
 extern const struct rz_sysc_init_data rzg3e_sys_init_data;
-- 
2.51.0

[PATCH 6.1.y-cip 02/11] soc: renesas: r9a09g056-sys: Populate max_register

[Ovidiu Panait]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit 4ff787433ba6d564b00334b4bfd6350f5b6f4bb3 upstream.

Populate max_register to avoid external aborts.

Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105070526.264445-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/soc/renesas/r9a09g056-sys.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c
index 3ad1422eba36..16b4e433c337 100644
--- a/drivers/soc/renesas/r9a09g056-sys.c
+++ b/drivers/soc/renesas/r9a09g056-sys.c
@@ -72,4 +72,5 @@ static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initco
 
 const struct rz_sysc_init_data rzv2n_sys_init_data = {
 	.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
+	.max_register = 0x170c,
 };
-- 
2.51.0

[PATCH 6.1.y-cip 03/11] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config

[Ovidiu Panait]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit c432180a7d95081353a96fd6d5bd75b0fc8a27c3 upstream.

Not all system controller registers are accessible from Linux. Accessing
such registers generates synchronous external abort. Populate the
readable_reg and writeable_reg members of the regmap config to inform the
regmap core which registers can be accessed. The list will need to be
updated whenever new system controller functionality is exported through
regmap.

Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105070526.264445-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/soc/renesas/r9a08g045-sysc.c |  69 ++++++++++++++++++
 drivers/soc/renesas/r9a09g047-sys.c  |  79 +++++++++++++++++++++
 drivers/soc/renesas/r9a09g056-sys.c  |  68 ++++++++++++++++++
 drivers/soc/renesas/r9a09g057-sys.c  | 101 +++++++++++++++++++++++++++
 drivers/soc/renesas/rz-sysc.c        |   2 +
 drivers/soc/renesas/rz-sysc.h        |   4 ++
 6 files changed, 323 insertions(+)

diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c
index 0504d4e68761..03d653d5cde5 100644
--- a/drivers/soc/renesas/r9a08g045-sysc.c
+++ b/drivers/soc/renesas/r9a08g045-sysc.c
@@ -6,10 +6,29 @@
  */
 
 #include <linux/bits.h>
+#include <linux/device.h>
 #include <linux/init.h>
 
 #include "rz-sysc.h"
 
+#define SYS_XSPI_MAP_STAADD_CS0		0x348
+#define SYS_XSPI_MAP_ENDADD_CS0		0x34c
+#define SYS_XSPI_MAP_STAADD_CS1		0x350
+#define SYS_XSPI_MAP_ENDADD_CS1		0x354
+#define SYS_GETH0_CFG			0x380
+#define SYS_GETH1_CFG			0x390
+#define SYS_PCIE_CFG			0x3a0
+#define SYS_PCIE_MON			0x3a4
+#define SYS_PCIE_ERR_MON		0x3ac
+#define SYS_PCIE_PHY			0x3b4
+#define SYS_I2C0_CFG			0x400
+#define SYS_I2C1_CFG			0x410
+#define SYS_I2C2_CFG			0x420
+#define SYS_I2C3_CFG			0x430
+#define SYS_I3C_CFG			0x440
+#define SYS_USB_PWRRDY			0xd70
+#define SYS_PCIE_RST_RSM_B		0xd74
+
 static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = {
 	.family = "RZ/G3S",
 	.id = 0x85e0447,
@@ -18,7 +37,57 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
 	.specific_id_mask = GENMASK(27, 0),
 };
 
+static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_XSPI_MAP_STAADD_CS0:
+	case SYS_XSPI_MAP_ENDADD_CS0:
+	case SYS_XSPI_MAP_STAADD_CS1:
+	case SYS_XSPI_MAP_ENDADD_CS1:
+	case SYS_GETH0_CFG:
+	case SYS_GETH1_CFG:
+	case SYS_PCIE_CFG:
+	case SYS_PCIE_MON:
+	case SYS_PCIE_ERR_MON:
+	case SYS_PCIE_PHY:
+	case SYS_I2C0_CFG:
+	case SYS_I2C1_CFG:
+	case SYS_I2C2_CFG:
+	case SYS_I2C3_CFG:
+	case SYS_I3C_CFG:
+	case SYS_USB_PWRRDY:
+	case SYS_PCIE_RST_RSM_B:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_XSPI_MAP_STAADD_CS0:
+	case SYS_XSPI_MAP_ENDADD_CS0:
+	case SYS_XSPI_MAP_STAADD_CS1:
+	case SYS_XSPI_MAP_ENDADD_CS1:
+	case SYS_PCIE_CFG:
+	case SYS_PCIE_PHY:
+	case SYS_I2C0_CFG:
+	case SYS_I2C1_CFG:
+	case SYS_I2C2_CFG:
+	case SYS_I2C3_CFG:
+	case SYS_I3C_CFG:
+	case SYS_USB_PWRRDY:
+	case SYS_PCIE_RST_RSM_B:
+		return true;
+	default:
+		return false;
+	}
+}
+
 const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
 	.soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
+	.readable_reg = rzg3s_regmap_readable_reg,
+	.writeable_reg = rzg3s_regmap_writeable_reg,
 	.max_register = 0xe20,
 };
diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c
index 2e8426c03050..e413b0eff9bf 100644
--- a/drivers/soc/renesas/r9a09g047-sys.c
+++ b/drivers/soc/renesas/r9a09g047-sys.c
@@ -29,6 +29,27 @@
 #define SYS_LSI_PRR_CA55_DIS		BIT(8)
 #define SYS_LSI_PRR_NPU_DIS		BIT(1)
 
+#define SYS_LSI_OTPTSU1TRMVAL0		0x330
+#define SYS_LSI_OTPTSU1TRMVAL1		0x334
+#define SYS_SPI_STAADDCS0		0x900
+#define SYS_SPI_ENDADDCS0		0x904
+#define SYS_SPI_STAADDCS1		0x908
+#define SYS_SPI_ENDADDCS1		0x90c
+#define SYS_VSP_CLK			0xe00
+#define SYS_GBETH0_CFG			0xf00
+#define SYS_GBETH1_CFG			0xf04
+#define SYS_PCIE_INTX_CH0		0x1000
+#define SYS_PCIE_MSI1_CH0		0x1004
+#define SYS_PCIE_MSI2_CH0		0x1008
+#define SYS_PCIE_MSI3_CH0		0x100c
+#define SYS_PCIE_MSI4_CH0		0x1010
+#define SYS_PCIE_MSI5_CH0		0x1014
+#define SYS_PCIE_PME_CH0		0x1018
+#define SYS_PCIE_ACK_CH0		0x101c
+#define SYS_PCIE_MISC_CH0		0x1020
+#define SYS_PCIE_MODE_CH0		0x1024
+#define SYS_ADC_CFG			0x1600
+
 static void rzg3e_sys_print_id(struct device *dev,
 				void __iomem *sysc_base,
 				struct soc_device_attribute *soc_dev_attr)
@@ -62,7 +83,65 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco
 	.print_id = rzg3e_sys_print_id,
 };
 
+static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_LSI_OTPTSU1TRMVAL0:
+	case SYS_LSI_OTPTSU1TRMVAL1:
+	case SYS_SPI_STAADDCS0:
+	case SYS_SPI_ENDADDCS0:
+	case SYS_SPI_STAADDCS1:
+	case SYS_SPI_ENDADDCS1:
+	case SYS_VSP_CLK:
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_SPI_STAADDCS0:
+	case SYS_SPI_ENDADDCS0:
+	case SYS_SPI_STAADDCS1:
+	case SYS_SPI_ENDADDCS1:
+	case SYS_VSP_CLK:
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
 const struct rz_sysc_init_data rzg3e_sys_init_data = {
 	.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
+	.readable_reg = rzg3e_regmap_readable_reg,
+	.writeable_reg = rzg3e_regmap_writeable_reg,
 	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c
index 16b4e433c337..42f5eff291fd 100644
--- a/drivers/soc/renesas/r9a09g056-sys.c
+++ b/drivers/soc/renesas/r9a09g056-sys.c
@@ -34,6 +34,24 @@
 #define SYS_RZV2N_FEATURE_C55		BIT(1)
 #define SYS_RZV2N_FEATURE_SEC		BIT(2)
 
+#define SYS_LSI_OTPTSU0TRMVAL0		0x320
+#define SYS_LSI_OTPTSU0TRMVAL1		0x324
+#define SYS_LSI_OTPTSU1TRMVAL0		0x330
+#define SYS_LSI_OTPTSU1TRMVAL1		0x334
+#define SYS_GBETH0_CFG			0xf00
+#define SYS_GBETH1_CFG			0xf04
+#define SYS_PCIE_INTX_CH0		0x1000
+#define SYS_PCIE_MSI1_CH0		0x1004
+#define SYS_PCIE_MSI2_CH0		0x1008
+#define SYS_PCIE_MSI3_CH0		0x100c
+#define SYS_PCIE_MSI4_CH0		0x1010
+#define SYS_PCIE_MSI5_CH0		0x1014
+#define SYS_PCIE_PME_CH0		0x1018
+#define SYS_PCIE_ACK_CH0		0x101c
+#define SYS_PCIE_MISC_CH0		0x1020
+#define SYS_PCIE_MODE_CH0		0x1024
+#define SYS_ADC_CFG			0x1600
+
 static void rzv2n_sys_print_id(struct device *dev,
 			       void __iomem *sysc_base,
 			       struct soc_device_attribute *soc_dev_attr)
@@ -70,7 +88,57 @@ static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initco
 	.print_id = rzv2n_sys_print_id,
 };
 
+static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_LSI_OTPTSU0TRMVAL0:
+	case SYS_LSI_OTPTSU0TRMVAL1:
+	case SYS_LSI_OTPTSU1TRMVAL0:
+	case SYS_LSI_OTPTSU1TRMVAL1:
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool rzv2n_regmap_writeable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
 const struct rz_sysc_init_data rzv2n_sys_init_data = {
 	.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
+	.readable_reg = rzv2n_regmap_readable_reg,
+	.writeable_reg = rzv2n_regmap_writeable_reg,
 	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c
index e3390e7c7fe5..827c718ac7c5 100644
--- a/drivers/soc/renesas/r9a09g057-sys.c
+++ b/drivers/soc/renesas/r9a09g057-sys.c
@@ -29,6 +29,35 @@
 #define SYS_LSI_PRR_GPU_DIS		BIT(0)
 #define SYS_LSI_PRR_ISP_DIS		BIT(4)
 
+#define SYS_LSI_OTPTSU0TRMVAL0		0x320
+#define SYS_LSI_OTPTSU0TRMVAL1		0x324
+#define SYS_LSI_OTPTSU1TRMVAL0		0x330
+#define SYS_LSI_OTPTSU1TRMVAL1		0x334
+#define SYS_GBETH0_CFG			0xf00
+#define SYS_GBETH1_CFG			0xf04
+#define SYS_PCIE_INTX_CH0		0x1000
+#define SYS_PCIE_MSI1_CH0		0x1004
+#define SYS_PCIE_MSI2_CH0		0x1008
+#define SYS_PCIE_MSI3_CH0		0x100c
+#define SYS_PCIE_MSI4_CH0		0x1010
+#define SYS_PCIE_MSI5_CH0		0x1014
+#define SYS_PCIE_PME_CH0		0x1018
+#define SYS_PCIE_ACK_CH0		0x101c
+#define SYS_PCIE_MISC_CH0		0x1020
+#define SYS_PCIE_MODE_CH0		0x1024
+#define SYS_PCIE_INTX_CH1		0x1030
+#define SYS_PCIE_MSI1_CH1		0x1034
+#define SYS_PCIE_MSI2_CH1		0x1038
+#define SYS_PCIE_MSI3_CH1		0x103c
+#define SYS_PCIE_MSI4_CH1		0x1040
+#define SYS_PCIE_MSI5_CH1		0x1044
+#define SYS_PCIE_PME_CH1		0x1048
+#define SYS_PCIE_ACK_CH1		0x104c
+#define SYS_PCIE_MISC_CH1		0x1050
+#define SYS_PCIE_MODE_CH1		0x1054
+#define SYS_PCIE_MODE			0x1060
+#define SYS_ADC_CFG			0x1600
+
 static void rzv2h_sys_print_id(struct device *dev,
 				void __iomem *sysc_base,
 				struct soc_device_attribute *soc_dev_attr)
@@ -62,7 +91,79 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initco
 	.print_id = rzv2h_sys_print_id,
 };
 
+static bool rzv2h_regmap_readable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_LSI_OTPTSU0TRMVAL0:
+	case SYS_LSI_OTPTSU0TRMVAL1:
+	case SYS_LSI_OTPTSU1TRMVAL0:
+	case SYS_LSI_OTPTSU1TRMVAL1:
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_PCIE_INTX_CH1:
+	case SYS_PCIE_MSI1_CH1:
+	case SYS_PCIE_MSI2_CH1:
+	case SYS_PCIE_MSI3_CH1:
+	case SYS_PCIE_MSI4_CH1:
+	case SYS_PCIE_MSI5_CH1:
+	case SYS_PCIE_PME_CH1:
+	case SYS_PCIE_ACK_CH1:
+	case SYS_PCIE_MISC_CH1:
+	case SYS_PCIE_MODE_CH1:
+	case SYS_PCIE_MODE:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool rzv2h_regmap_writeable_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case SYS_GBETH0_CFG:
+	case SYS_GBETH1_CFG:
+	case SYS_PCIE_INTX_CH0:
+	case SYS_PCIE_MSI1_CH0:
+	case SYS_PCIE_MSI2_CH0:
+	case SYS_PCIE_MSI3_CH0:
+	case SYS_PCIE_MSI4_CH0:
+	case SYS_PCIE_MSI5_CH0:
+	case SYS_PCIE_PME_CH0:
+	case SYS_PCIE_ACK_CH0:
+	case SYS_PCIE_MISC_CH0:
+	case SYS_PCIE_MODE_CH0:
+	case SYS_PCIE_INTX_CH1:
+	case SYS_PCIE_MSI1_CH1:
+	case SYS_PCIE_MSI2_CH1:
+	case SYS_PCIE_MSI3_CH1:
+	case SYS_PCIE_MSI4_CH1:
+	case SYS_PCIE_MSI5_CH1:
+	case SYS_PCIE_PME_CH1:
+	case SYS_PCIE_ACK_CH1:
+	case SYS_PCIE_MISC_CH1:
+	case SYS_PCIE_MODE_CH1:
+	case SYS_PCIE_MODE:
+	case SYS_ADC_CFG:
+		return true;
+	default:
+		return false;
+	}
+}
+
 const struct rz_sysc_init_data rzv2h_sys_init_data = {
 	.soc_id_init_data = &rzv2h_sys_soc_id_init_data,
+	.readable_reg = rzv2h_regmap_readable_reg,
+	.writeable_reg = rzv2h_regmap_writeable_reg,
 	.max_register = 0x170c,
 };
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index 9f79e299e6f4..19c1e666279b 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -140,6 +140,8 @@ static int rz_sysc_probe(struct platform_device *pdev)
 	regmap_cfg->val_bits = 32;
 	regmap_cfg->fast_io = true;
 	regmap_cfg->max_register = data->max_register;
+	regmap_cfg->readable_reg = data->readable_reg;
+	regmap_cfg->writeable_reg = data->writeable_reg;
 
 	regmap = devm_regmap_init_mmio(dev, sysc->base, regmap_cfg);
 	if (IS_ERR(regmap))
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index 8eec355d5d56..88929bf21cb1 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -34,10 +34,14 @@ struct rz_sysc_soc_id_init_data {
 /**
  * struct rz_sysc_init_data - RZ SYSC initialization data
  * @soc_id_init_data: RZ SYSC SoC ID initialization data
+ * @writeable_reg: Regmap writeable register check function
+ * @readable_reg: Regmap readable register check function
  * @max_register: Maximum SYSC register offset to be used by the regmap config
  */
 struct rz_sysc_init_data {
 	const struct rz_sysc_soc_id_init_data *soc_id_init_data;
+	bool (*writeable_reg)(struct device *dev, unsigned int reg);
+	bool (*readable_reg)(struct device *dev, unsigned int reg);
 	u32 max_register;
 };
 
-- 
2.51.0

[PATCH 6.1.y-cip 04/11] PM: domains: Add RZ/V2H compatible to PM domain detach list

[Ovidiu Panait]

Add Renesas RZ/V2H compatible to the PM domain detach list in
dev_pm_domain_allow_detach_on_unbind_cleanup(). This fixes asynchronous
aborts when unbinding the TSU devices.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/base/power/common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
index f1fd50d0efb9..8e002aa131f0 100644
--- a/drivers/base/power/common.c
+++ b/drivers/base/power/common.c
@@ -245,6 +245,7 @@ bool dev_pm_domain_allow_detach_on_unbind_cleanup(void)
 		"renesas,r9a07g044", /* Renesas RZ/G2{L, LC} */
 		"renesas,r9a07g054", /* Renesas RZ/V2L */
 		"renesas,r9a08g045", /* Renesas RZ/G3S */
+		"renesas,r9a09g057", /* Renesas RZ/V2H */
 		NULL
 	};
 
-- 
2.51.0

[PATCH 6.1.y-cip 05/11] dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit

[Ovidiu Panait]

From: John Madieu <john.madieu.xa@bp.renesas.com>

commit caf41eb4575ddac61dd0f6d4a6108bb7ab9fc408 upstream.

The Renesas RZ/G3E SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing a single
dedicated channel (channel 1) for temperature sensing.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Link: https://lore.kernel.org/r/20250917170202.197929-2-john.madieu.xa@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 .../thermal/renesas,r9a09g047-tsu.yaml        | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
new file mode 100644
index 000000000000..8d3f3c24f0f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E Temperature Sensor Unit (TSU)
+
+maintainers:
+  - John Madieu <john.madieu.xa@bp.renesas.com>
+
+description:
+  The Temperature Sensor Unit (TSU) is an integrated thermal sensor that
+  monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides
+  real-time temperature measurements for thermal management.
+
+properties:
+  compatible:
+    const: renesas,r9a09g047-tsu
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Conversion complete interrupt signal (pulse)
+      - description: Comparison result interrupt signal (level)
+
+  interrupt-names:
+    items:
+      - const: adi
+      - const: adcmpi
+
+  "#thermal-sensor-cells":
+    const: 0
+
+  renesas,tsu-trim:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to system controller
+          - description: offset of trim registers
+    description:
+      Phandle and offset to the system controller containing the TSU
+      calibration trim values. The offset points to the first trim register
+      (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located
+      at offset + 4.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - power-domains
+  - interrupts
+  - interrupt-names
+  - "#thermal-sensor-cells"
+  - renesas,tsu-trim
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    thermal-sensor@14002000 {
+        compatible = "renesas,r9a09g047-tsu";
+        reg = <0x14002000 0x1000>;
+        clocks = <&cpg CPG_MOD 0x10a>;
+        resets = <&cpg 0xf8>;
+        power-domains = <&cpg>;
+        interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "adi", "adcmpi";
+        #thermal-sensor-cells = <0>;
+        renesas,tsu-trim = <&sys 0x330>;
+    };
-- 
2.51.0

[PATCH 6.1.y-cip 06/11] thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC

[Ovidiu Panait]

From: John Madieu <john.madieu.xa@bp.renesas.com>

commit 19d3a401a617c68e9487f55b9f2efe213f8f949d upstream.

The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed
to monitor the chip's junction temperature. This sensor is connected to
channel 1 of the APB port clock/reset and provides temperature measurements.

It also requires calibration values stored in the system controller registers
for accurate temperature measurement. Add a driver for the Renesas RZ/G3E TSU.

[ dlezcano: Fixed conflict with "renesas: Add support for RZ/G3S" ]

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250917170202.197929-3-john.madieu.xa@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 MAINTAINERS              | 7 +++++++
 drivers/thermal/Kconfig  | 7 +++++++
 drivers/thermal/Makefile | 1 +
 3 files changed, 15 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 061d208b5a9f..6ec53b8ac3b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17690,6 +17690,13 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml
 F:	drivers/thermal/renesas/rzg3s_thermal.c
 
+RENESAS RZ/G3E THERMAL SENSOR UNIT DRIVER
+M:	John Madieu <john.madieu.xa@bp.renesas.com>
+L:	linux-pm@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
+F:	drivers/thermal/renesas/rzg3e_thermal.c
+
 RESET CONTROLLER FRAMEWORK
 M:	Philipp Zabel <p.zabel@pengutronix.de>
 S:	Maintained
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 4bd995d9eb08..161e887bf13c 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -373,6 +373,13 @@ config RZG3S_THERMAL
 	  Enable this to plug the RZ/G3S thermal sensor driver into the Linux
 	  thermal framework.
 
+config RZG3E_THERMAL
+	tristate "Renesas RZ/G3E thermal driver"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	help
+	 Enable this to plug the RZ/G3E thermal sensor driver into the Linux
+	 thermal framework
+
 config KIRKWOOD_THERMAL
 	tristate "Temperature sensor on Marvell Kirkwood SoCs"
 	depends on MACH_KIRKWOOD || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index a3498d4cb553..5bda83243bae 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_ROCKCHIP_THERMAL)	+= rockchip_thermal.o
 obj-$(CONFIG_RCAR_THERMAL)	+= rcar_thermal.o
 obj-$(CONFIG_RCAR_GEN3_THERMAL)	+= rcar_gen3_thermal.o
 obj-$(CONFIG_RZG2L_THERMAL)	+= rzg2l_thermal.o
+obj-$(CONFIG_RZG3E_THERMAL)	+= rzg3e_thermal.o
 obj-$(CONFIG_RZG3S_THERMAL)	+= rzg3s_thermal.o
 obj-$(CONFIG_KIRKWOOD_THERMAL)  += kirkwood_thermal.o
 obj-y				+= samsung/
-- 
2.51.0

[PATCH 6.1.y-cip 07/11] thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC

[Ovidiu Panait]

From: John Madieu <john.madieu.xa@bp.renesas.com>

commit dc67521c20b701b5237ff486ae078829dc1f8fea upstream.

When applied the change commit 19d3a401a617, a conflict appeared
resulting into a manual fix. However the new file rzg3e_thermal.c was
not added but stayed locally in source tree and miss to be merged with
the entire change.

Fix this by adding the file back.

Fixes: 19d3a401a617 ("Add thermal driver for the Renesas RZ/G3E SoC")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202509272225.sARVqv2G-lkp@intel.com
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
[OP:
 - included "thermal_hwmon.h" instead of "../thermal_hwmon.h"
 - replaced thermal_zone_device_priv(rz) with tz->devdata as
   thermal_zone_device_priv is not present in v6.1 CIP
 - used devm_reset_control_get_exclusive() + reset_control_deassert() +
   devm_add_action_or_reset() instead of
   devm_reset_control_get_exclusive_deasserted() as the latter is not
   available in v6.1 CIP; added rzg3e_thermal_reset_assert() action
   function for this
 - used thermal_add_hwmon_sysfs() + devm_add_action_or_reset() instead
   of devm_thermal_add_hwmon_sysfs() as the latter is not available in
   v6.1 CIP; added rzg3e_thermal_rem_hwmon_sysfs() for this]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/thermal/rzg3e_thermal.c | 572 ++++++++++++++++++++++++++++++++
 1 file changed, 572 insertions(+)
 create mode 100644 drivers/thermal/rzg3e_thermal.c

diff --git a/drivers/thermal/rzg3e_thermal.c b/drivers/thermal/rzg3e_thermal.c
new file mode 100644
index 000000000000..f5958f1ff24f
--- /dev/null
+++ b/drivers/thermal/rzg3e_thermal.c
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E TSU Temperature Sensor Unit
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+#include <linux/clk.h>
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+#include <linux/units.h>
+
+#include "thermal_hwmon.h"
+
+/* TSU Register offsets and bits */
+#define TSU_SSUSR		0x00
+#define TSU_SSUSR_EN_TS		BIT(0)
+#define TSU_SSUSR_ADC_PD_TS	BIT(1)
+#define TSU_SSUSR_SOC_TS_EN	BIT(2)
+
+#define TSU_STRGR		0x04
+#define TSU_STRGR_ADST		BIT(0)
+
+#define TSU_SOSR1		0x08
+#define TSU_SOSR1_ADCT_8	0x03
+#define TSU_SOSR1_ADCS		BIT(4)
+#define TSU_SOSR1_OUTSEL	BIT(9)
+
+#define TSU_SCRR		0x10
+#define TSU_SCRR_OUT12BIT_TS	GENMASK(11, 0)
+
+#define TSU_SSR			0x14
+#define TSU_SSR_CONV		BIT(0)
+
+#define TSU_CMSR		0x18
+#define TSU_CMSR_CMPEN		BIT(0)
+
+#define TSU_LLSR		0x1C
+#define TSU_ULSR		0x20
+
+#define TSU_SISR		0x30
+#define TSU_SISR_ADF		BIT(0)
+#define TSU_SISR_CMPF		BIT(1)
+
+#define TSU_SIER		0x34
+#define TSU_SIER_CMPIE		BIT(1)
+
+#define TSU_SICR		0x38
+#define TSU_SICR_ADCLR		BIT(0)
+#define TSU_SICR_CMPCLR	BIT(1)
+
+/* Temperature calculation constants from datasheet */
+#define TSU_TEMP_D		(-41)
+#define TSU_TEMP_E		126
+#define TSU_CODE_MAX		0xFFF
+
+/* Timing specifications from datasheet */
+#define TSU_POWERUP_TIME_US	120	/* 120T at 1MHz sensor clock per datasheet */
+#define TSU_CONV_TIME_US	50	/* Per sample conversion time */
+#define TSU_POLL_DELAY_US	10	/* Polling interval */
+#define TSU_MIN_CLOCK_RATE	24000000  /* TSU_PCLK minimum 24MHz */
+
+/**
+ * struct rzg3e_thermal_priv - RZ/G3E TSU private data
+ * @base: TSU register base
+ * @dev: device pointer
+ * @syscon: regmap for calibration values
+ * @zone: thermal zone device
+ * @rstc: reset control
+ * @trmval0: calibration value 0 (b)
+ * @trmval1: calibration value 1 (c)
+ * @trim_offset: offset for trim registers in syscon
+ * @lock: protects hardware access during conversions
+ */
+struct rzg3e_thermal_priv {
+	void __iomem *base;
+	struct device *dev;
+	struct regmap *syscon;
+	struct thermal_zone_device *zone;
+	struct reset_control *rstc;
+	u16 trmval0;
+	u16 trmval1;
+	u32 trim_offset;
+	struct mutex lock;
+};
+
+static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv)
+{
+	u32 val;
+	int ret;
+
+	/* Clear any pending interrupts */
+	writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
+
+	/* Disable all interrupts during setup */
+	writel(0, priv->base + TSU_SIER);
+
+	/*
+	 * Power-on sequence per datasheet 7.11.9.1:
+	 * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS
+	 */
+	val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS;
+	writel(val, priv->base + TSU_SSUSR);
+
+	/* Wait for sensor stabilization per datasheet 7.11.7.1 */
+	usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10);
+
+	/* Configure for average mode with 8 samples */
+	val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8;
+	writel(val, priv->base + TSU_SOSR1);
+
+	/* Ensure we're in single scan mode (default) */
+	val = readl(priv->base + TSU_SOSR1);
+	if (val & TSU_SOSR1_ADCS) {
+		dev_err(priv->dev, "Invalid scan mode setting\n");
+		return -EINVAL;
+	}
+
+	/* Wait for any ongoing conversion to complete */
+	ret = readl_poll_timeout(priv->base + TSU_SSR, val,
+				 !(val & TSU_SSR_CONV),
+				 TSU_POLL_DELAY_US,
+				 USEC_PER_MSEC);
+	if (ret) {
+		dev_err(priv->dev, "Timeout waiting for conversion\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv)
+{
+	/* Disable all interrupts */
+	writel(0, priv->base + TSU_SIER);
+
+	/* Clear pending interrupts */
+	writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
+
+	/* Power down sequence per datasheet */
+	writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR);
+}
+
+/*
+ * Convert 12-bit sensor code to temperature in millicelsius
+ * Formula from datasheet 7.11.7.8:
+ * T(°C) = ((e - d) / (c - b)) * (a - b) + d
+ * where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126
+ */
+static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16 code)
+{
+	int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE;
+	int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE;
+	s64 numerator, denominator;
+	int temp_mc;
+
+	numerator = (temp_e_mc - temp_d_mc) * (s64)(code - priv->trmval0);
+	denominator = priv->trmval1 - priv->trmval0;
+
+	temp_mc = div64_s64(numerator, denominator) + temp_d_mc;
+
+	return clamp(temp_mc, temp_d_mc, temp_e_mc);
+}
+
+/*
+ * Convert temperature in millicelsius to 12-bit sensor code
+ * Formula from datasheet 7.11.7.9 (inverse of above)
+ */
+static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int temp_mc)
+{
+	int temp_e_mc = TSU_TEMP_E * MILLIDEGREE_PER_DEGREE;
+	int temp_d_mc = TSU_TEMP_D * MILLIDEGREE_PER_DEGREE;
+	s64 numerator, denominator;
+	s64 code;
+
+	numerator = (temp_mc - temp_d_mc) * (priv->trmval1 - priv->trmval0);
+	denominator = temp_e_mc - temp_d_mc;
+
+	code = div64_s64(numerator, denominator) + priv->trmval0;
+
+	return clamp_val(code, 0, TSU_CODE_MAX);
+}
+
+static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+	struct rzg3e_thermal_priv *priv = tz->devdata;
+	u32 status, code;
+	int ret, timeout;
+
+	ret = pm_runtime_resume_and_get(priv->dev);
+	if (ret < 0)
+		return ret;
+
+	guard(mutex)(&priv->lock);
+
+	/* Clear any previous conversion status */
+	writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
+
+	/* Start single conversion */
+	writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
+
+	/* Wait for conversion completion - 8 samples at ~50us each */
+	timeout = TSU_CONV_TIME_US * 8 * 2;  /* Double for margin */
+	ret = readl_poll_timeout(priv->base + TSU_SISR, status,
+				 status & TSU_SISR_ADF,
+				 TSU_POLL_DELAY_US, timeout);
+	if (ret) {
+		dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status);
+		goto out;
+	}
+
+	/* Read the averaged result and clear the complete flag */
+	code = readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS;
+	writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
+
+	/* Convert to temperature */
+	*temp = rzg3e_thermal_code_to_temp(priv, code);
+
+	dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n",
+		*temp, *temp / 1000, abs(*temp) % 1000, code);
+
+out:
+	pm_runtime_mark_last_busy(priv->dev);
+	pm_runtime_put_autosuspend(priv->dev);
+	return ret;
+}
+
+static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz,
+				   int low, int high)
+{
+	struct rzg3e_thermal_priv *priv = tz->devdata;
+	u16 low_code, high_code;
+	u32 val;
+	int ret;
+
+	/* Hardware requires low < high */
+	if (low >= high)
+		return -EINVAL;
+
+	ret = pm_runtime_resume_and_get(priv->dev);
+	if (ret < 0)
+		return ret;
+
+	guard(mutex)(&priv->lock);
+
+	/* Convert temperatures to codes */
+	low_code = rzg3e_thermal_temp_to_code(priv, low);
+	high_code = rzg3e_thermal_temp_to_code(priv, high);
+
+	dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n",
+		low, high, low_code, high_code);
+
+	/* Disable comparison during reconfiguration */
+	writel(0, priv->base + TSU_SIER);
+	writel(0, priv->base + TSU_CMSR);
+
+	/* Clear any pending comparison interrupts */
+	writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
+
+	/* Set trip points */
+	writel(low_code, priv->base + TSU_LLSR);
+	writel(high_code, priv->base + TSU_ULSR);
+
+	/*
+	 * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4
+	 * Comparison uses averaged data
+	 */
+	val = readl(priv->base + TSU_SOSR1);
+	val |= TSU_SOSR1_OUTSEL;
+	writel(val, priv->base + TSU_SOSR1);
+
+	/* Enable comparison with "out of range" mode (CMPCOND=0) */
+	writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR);
+
+	/* Unmask compare IRQ and start a conversion to evaluate window */
+	writel(TSU_SIER_CMPIE, priv->base + TSU_SIER);
+	writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
+
+	pm_runtime_mark_last_busy(priv->dev);
+	pm_runtime_put_autosuspend(priv->dev);
+
+	return 0;
+}
+
+static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data)
+{
+	struct rzg3e_thermal_priv *priv = data;
+
+	dev_dbg(priv->dev, "Temperature threshold crossed\n");
+
+	/* Notify thermal framework to re-evaluate trip points */
+	thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t rzg3e_thermal_irq(int irq, void *data)
+{
+	struct rzg3e_thermal_priv *priv = data;
+	u32 status;
+
+	status = readl(priv->base + TSU_SISR);
+
+	/* Check if comparison interrupt occurred */
+	if (status & TSU_SISR_CMPF) {
+		/* Clear irq flag and disable interrupt until reconfigured */
+		writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
+		writel(0, priv->base + TSU_SIER);
+
+		return IRQ_WAKE_THREAD;
+	}
+
+	return IRQ_NONE;
+}
+
+static const struct thermal_zone_device_ops rzg3e_tz_ops = {
+	.get_temp = rzg3e_thermal_get_temp,
+	.set_trips = rzg3e_thermal_set_trips,
+};
+
+static int rzg3e_thermal_get_calibration(struct rzg3e_thermal_priv *priv)
+{
+	u32 val;
+	int ret;
+
+	/* Read calibration values from syscon */
+	ret = regmap_read(priv->syscon, priv->trim_offset, &val);
+	if (ret)
+		return ret;
+	priv->trmval0 = val & GENMASK(11, 0);
+
+	ret = regmap_read(priv->syscon, priv->trim_offset + 4, &val);
+	if (ret)
+		return ret;
+	priv->trmval1 = val & GENMASK(11, 0);
+
+	/* Validate calibration data */
+	if (!priv->trmval0 || !priv->trmval1 ||
+	    priv->trmval0 == priv->trmval1 ||
+	    priv->trmval0 == 0xFFF || priv->trmval1 == 0xFFF) {
+		dev_err(priv->dev, "Invalid calibration: b=0x%03x, c=0x%03x\n",
+			priv->trmval0, priv->trmval1);
+		return -EINVAL;
+	}
+
+	dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
+		priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
+
+	return 0;
+}
+
+static int rzg3e_thermal_parse_dt(struct rzg3e_thermal_priv *priv)
+{
+	struct device_node *np = priv->dev->of_node;
+	u32 offset;
+
+	priv->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset);
+	if (IS_ERR(priv->syscon))
+		return dev_err_probe(priv->dev, PTR_ERR(priv->syscon),
+				     "Failed to parse renesas,tsu-trim\n");
+
+	priv->trim_offset = offset;
+	return 0;
+}
+
+static void rzg3e_thermal_reset_assert(void *data)
+{
+	reset_control_assert(data);
+}
+
+static void rzg3e_thermal_rem_hwmon_sysfs(void *data)
+{
+	thermal_remove_hwmon_sysfs(data);
+}
+
+static int rzg3e_thermal_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rzg3e_thermal_priv *priv;
+	struct clk *clk;
+	int irq, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = devm_mutex_init(dev, &priv->lock);
+	if (ret)
+		return ret;
+	platform_set_drvdata(pdev, priv);
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	/* Parse device tree for trim register info */
+	ret = rzg3e_thermal_parse_dt(priv);
+	if (ret)
+		return ret;
+
+	/* Get clock to verify frequency - clock is managed by power domain */
+	clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(dev, PTR_ERR(clk),
+				     "Failed to get clock\n");
+
+	if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE)
+		return dev_err_probe(dev, -EINVAL,
+				     "Clock rate %lu Hz too low (min %u Hz)\n",
+				     clk_get_rate(clk), TSU_MIN_CLOCK_RATE);
+
+	priv->rstc = devm_reset_control_get_exclusive(dev, NULL);
+	if (IS_ERR(priv->rstc))
+		return dev_err_probe(dev, PTR_ERR(priv->rstc),
+				     "Failed to get reset control!\n");
+
+	ret = reset_control_deassert(priv->rstc);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(dev, rzg3e_thermal_reset_assert, priv->rstc);
+	if (ret)
+		return ret;
+
+	/* Get calibration data */
+	ret = rzg3e_thermal_get_calibration(priv);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to get valid calibration data\n");
+
+	/* Get comparison interrupt */
+	irq = platform_get_irq_byname(pdev, "adcmpi");
+	if (irq < 0)
+		return irq;
+
+	/* Enable runtime PM */
+	pm_runtime_set_autosuspend_delay(dev, 1000);
+	pm_runtime_use_autosuspend(dev);
+	devm_pm_runtime_enable(dev);
+
+	/* Initial hardware setup */
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Runtime resume failed\n");
+
+	/* Register thermal zone - this will trigger DT parsing */
+	priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops);
+	if (IS_ERR(priv->zone)) {
+		ret = PTR_ERR(priv->zone);
+		dev_err(dev, "Failed to register thermal zone: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	/* Request threaded IRQ for comparison interrupt */
+	ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq,
+					rzg3e_thermal_irq_thread,
+					IRQF_ONESHOT, "rzg3e_thermal", priv);
+	if (ret) {
+		dev_err(dev, "Failed to request IRQ: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	/* Add hwmon sysfs interface */
+	ret = thermal_add_hwmon_sysfs(priv->zone);
+	if (ret) {
+		dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
+	} else {
+		ret = devm_add_action_or_reset(dev,
+					       rzg3e_thermal_rem_hwmon_sysfs,
+					       priv->zone);
+		if (ret)
+			goto err_pm_put;
+	}
+
+	pm_runtime_mark_last_busy(dev);
+	pm_runtime_put_autosuspend(dev);
+
+	dev_info(dev, "RZ/G3E thermal sensor registered\n");
+
+	return 0;
+
+err_pm_put:
+	pm_runtime_put_sync(dev);
+	return ret;
+}
+
+static int rzg3e_thermal_runtime_suspend(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	rzg3e_thermal_power_off(priv);
+	return 0;
+}
+
+static int rzg3e_thermal_runtime_resume(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	return rzg3e_thermal_power_on(priv);
+}
+
+static int rzg3e_thermal_suspend(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+
+	/* If device is active, power it off */
+	if (pm_runtime_active(dev))
+		rzg3e_thermal_power_off(priv);
+
+	/* Assert reset to ensure clean state after resume */
+	reset_control_assert(priv->rstc);
+
+	return 0;
+}
+
+static int rzg3e_thermal_resume(struct device *dev)
+{
+	struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
+	int ret;
+
+	/* Deassert reset */
+	ret = reset_control_deassert(priv->rstc);
+	if (ret) {
+		dev_err(dev, "Failed to deassert reset: %d\n", ret);
+		return ret;
+	}
+
+	/* If device was active before suspend, power it back on */
+	if (pm_runtime_active(dev))
+		return rzg3e_thermal_power_on(priv);
+
+	return 0;
+}
+
+static const struct dev_pm_ops rzg3e_thermal_pm_ops = {
+	RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend,
+		       rzg3e_thermal_runtime_resume, NULL)
+	SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume)
+};
+
+static const struct of_device_id rzg3e_thermal_dt_ids[] = {
+	{ .compatible = "renesas,r9a09g047-tsu" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids);
+
+static struct platform_driver rzg3e_thermal_driver = {
+	.driver = {
+		.name = "rzg3e_thermal",
+		.of_match_table = rzg3e_thermal_dt_ids,
+		.pm = pm_ptr(&rzg3e_thermal_pm_ops),
+	},
+	.probe = rzg3e_thermal_probe,
+};
+module_platform_driver(rzg3e_thermal_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver");
+MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>");
+MODULE_LICENSE("GPL");
-- 
2.51.0

[PATCH 6.1.y-cip 08/11] arm64: defconfig: Enable the Renesas RZ/G3E thermal driver

[Ovidiu Panait]

From: John Madieu <john.madieu.xa@bp.renesas.com>

commit caf433bb59db842b41f57e4d0088ce0f76bb302a upstream.

Enable the Renesas RZ/G3E thermal driver, as used on the Renesas
RZ/G3E SMARC EVK board.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250917170202.197929-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 212345c2b54d..911fe95af244 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -609,6 +609,7 @@ CONFIG_ROCKCHIP_THERMAL=m
 CONFIG_RCAR_THERMAL=y
 CONFIG_RCAR_GEN3_THERMAL=y
 CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3E_THERMAL=y
 CONFIG_RZG3S_THERMAL=m
 CONFIG_ARMADA_THERMAL=y
 CONFIG_BCM2711_THERMAL=m
-- 
2.51.0

[PATCH 6.1.y-cip 09/11] clk: renesas: r9a09g057: Add clock and reset entries for TSU

[Ovidiu Panait]

commit 919bf298dc9fe2cee5abfacb281fb201cda65a44 upstream.

Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2H (R9A09G057) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/clk/renesas/r9a09g057-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 7595632e3918..007dbbe08eb3 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -356,6 +356,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(3, BIT(4))),
 	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
 						BUS_MSTOP(3, BIT(4))),
+	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,
+						BUS_MSTOP(5, BIT(2))),
+	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
+						BUS_MSTOP(2, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -418,6 +422,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */
 	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */
 	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */
+	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */
+	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
-- 
2.51.0

[PATCH 6.1.y-cip 10/11] arm64: dts: renesas: r9a09g057: Move interrupt-parent to root node

[Ovidiu Panait]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

commit 098da100b309be7f3698139ee60c7cfea6a13950 upstream.

Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/87ecrw8o87.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 3eaa9b2698af..925df24693b3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -12,6 +12,7 @@ / {
 	compatible = "renesas,r9a09g057";
 	#address-cells = <2>;
 	#size-cells = <2>;
+	interrupt-parent = <&gic>;
 
 	audio_extal_clk: audio-clk {
 		compatible = "fixed-clock";
@@ -126,7 +127,6 @@ rtxin_clk: rtxin-clk {
 
 	soc: soc {
 		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
@@ -1177,11 +1177,11 @@ stmmac_axi_setup: stmmac-axi-config {
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
 	};
 };
-- 
2.51.0

[PATCH 6.1.y-cip 11/11] arm64: dts: renesas: r9a09g057: Add TSU nodes

[Ovidiu Panait]

commit 1f77aced8c5c6f69566e69f63c3a6c1960f7fc87 upstream.

The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing:
- TSU0, which is located near the DRP-AI block
- TSU1, which is located near the CPU and DRP-AI block

Since TSU1 is physically closer the CPU and the highest temperature
spot, it is used for CPU throttling through a passive trip and cooling
map. TSU0 is configured only with a critical trip.

Add TSU nodes along with thermal zones and keep them enabled in the SoC
DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-4-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[OP: Before commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a
"syscon" compatible"), it was mandatory for the system controller node
to have the "syscon" fallback commpatible to be able to read data from it.
Therefore, add "syscon" fallback compatible to system-controller node, so that
TSU can access calibration data using syscon_regmap_lookup_by_phandle_args().]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 77 +++++++++++++++++++++-
 1 file changed, 76 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 925df24693b3..dd2260f15a90 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -65,6 +65,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -75,6 +76,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -85,6 +87,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -95,6 +98,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -245,12 +249,38 @@ cpg: clock-controller@10420000 {
 		};
 
 		sys: system-controller@10430000 {
-			compatible = "renesas,r9a09g057-sys";
+			compatible = "renesas,r9a09g057-sys", "syscon";
 			reg = <0 0x10430000 0 0x10000>;
 			clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
 			resets = <&cpg 0x30>;
 		};
 
+		tsu0: thermal@11000000 {
+			compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
+			reg = <0 0x11000000 0 0x1000>;
+			interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x109>;
+			resets = <&cpg 0xf7>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x320>;
+		};
+
+		tsu1: thermal@14002000 {
+			compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
+			reg = <0 0x14002000 0 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x10a>;
+			resets = <&cpg 0xf8>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x330>;
+		};
+
 		xspi: spi@11030000 {
 			compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
 			reg = <0 0x11030000 0 0x10000>,
@@ -1175,6 +1205,51 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		sensor1_thermal: sensor1-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu0>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor2_thermal: sensor2-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu1>;
+
+			cooling-maps {
+				map0 {
+					trip = <&sensor2_target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				sensor2_target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.51.0

RE: [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support

[nobuhiro.iwamatsu.x90]

Hi all,

> -----Original Message-----
> From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Sent: Wednesday, January 28, 2026 10:25 PM
> To: cip-dev@lists.cip-project.org; pavel@nabladev.com; iwamatsu nobuhiro(岩
> 松 信洋 □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> Subject: [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support
> 
> Hi,
> 
> This series adds TSU support for the Renesas RZ/V2H SoC.
> 
> All patches, except for patch 4/11, were cherry-picked from mainline kernel.
> 
> Patch 4/11 is needed to fix asynchronous aborts during unbind. See the
> MSTOP series [1] for more details.
> 
> [1]
> https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.beznea.uj
> @bp.renesas.com/
> 
> Best regards,
> Ovidiu


I reviewed this series, looks good to me.
I can applyt this patch if there are no other comments and no issues on CI.
 https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2293415029

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

Best regards,
  Nobuhiro

> 
> Claudiu Beznea (2):
>   soc: renesas: r9a09g056-sys: Populate max_register
>   soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap
>     config
> 
> John Madieu (5):
>   soc: renesas: rz-sysc: Add syscon/regmap support
>   dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
>   thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas
>     RZ/G3E SoC
>   thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas
>     RZ/G3E SoC
>   arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
> 
> Kuninori Morimoto (1):
>   arm64: dts: renesas: r9a09g057: Move interrupt-parent to root node
> 
> Ovidiu Panait (3):
>   PM: domains: Add RZ/V2H compatible to PM domain detach list
>   clk: renesas: r9a09g057: Add clock and reset entries for TSU
>   arm64: dts: renesas: r9a09g057: Add TSU nodes
> 
>  .../thermal/renesas,r9a09g047-tsu.yaml        |  87 +++
>  MAINTAINERS                                   |   7 +
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  89 ++-
>  arch/arm64/configs/defconfig                  |   1 +
>  drivers/base/power/common.c                   |   1 +
>  drivers/clk/renesas/r9a09g057-cpg.c           |   6 +
>  drivers/soc/renesas/Kconfig                   |   1 +
>  drivers/soc/renesas/r9a08g045-sysc.c          |  70 +++
>  drivers/soc/renesas/r9a09g047-sys.c           |  80 +++
>  drivers/soc/renesas/r9a09g056-sys.c           |  69 +++
>  drivers/soc/renesas/r9a09g057-sys.c           | 102 ++++
>  drivers/soc/renesas/rz-sysc.c                 |  32 +-
>  drivers/soc/renesas/rz-sysc.h                 |   6 +
>  drivers/thermal/Kconfig                       |   7 +
>  drivers/thermal/Makefile                      |   1 +
>  drivers/thermal/rzg3e_thermal.c               | 572
> ++++++++++++++++++
>  16 files changed, 1123 insertions(+), 8 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
>  create mode 100644 drivers/thermal/rzg3e_thermal.c
> 
> --
> 2.51.0

RE: [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support

[nobuhiro.iwamatsu.x90]

Hi all,

> -----Original Message-----
> From: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> Sent: Thursday, January 29, 2026 5:11 PM
> To: 'Ovidiu Panait' <ovidiu.panait.rb@renesas.com>;
> cip-dev@lists.cip-project.org; pavel@nabladev.com
> Subject: RE: [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support
> 
> Hi all,
> 
> > -----Original Message-----
> > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > Sent: Wednesday, January 28, 2026 10:25 PM
> > To: cip-dev@lists.cip-project.org; pavel@nabladev.com; iwamatsu
> > nobuhiro(岩
> > 松 信洋 □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> > Subject: [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support
> >
> > Hi,
> >
> > This series adds TSU support for the Renesas RZ/V2H SoC.
> >
> > All patches, except for patch 4/11, were cherry-picked from mainline kernel.
> >
> > Patch 4/11 is needed to fix asynchronous aborts during unbind. See the
> > MSTOP series [1] for more details.
> >
> > [1]
> > https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.bezne
> > a.uj
> > @bp.renesas.com/
> >
> > Best regards,
> > Ovidiu
> 
> 
> I reviewed this series, looks good to me.
> I can applyt this patch if there are no other comments and no issues on CI.
>  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2293415029
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
> 
> Best regards,
>   Nobuhiro
> 

Applied and pushed, thanks.

Best regards,
  Nobuhiro

Re: [cip-dev] [PATCH 6.1.y-cip 01/11] soc: renesas: rz-sysc: Add syscon/regmap support

[Pavel Machek]

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Hi!

> commit 2da2740fb9c8e26b6b5e20d74f2ed1d49824236d upstream.
> 
> The RZ/G3E system controller has various registers that control or report
> some properties specific to individual IPs. The regmap is registered as a
> syscon device to allow these IP drivers to access the registers through the
> regmap API.
> 
> As other RZ SoCs might have custom read/write callbacks or max-offsets,
> register a custom regmap configuration.
> 
> [claudiu.beznea:
>  - do not check the match->data validity in rz_sysc_probe() as it is
>    always valid
>  - dinamically allocate regmap_cfg]

...

> +++ b/drivers/soc/renesas/rz-sysc.c
> @@ -100,14 +104,23 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match);
>  
>  static int rz_sysc_probe(struct platform_device *pdev)
>  {
> +	const struct rz_sysc_init_data *data;
>  	const struct of_device_id *match;
>  	struct device *dev = &pdev->dev;
> +	struct regmap *regmap;
>  	struct rz_sysc *sysc;
> +	int ret;
> +
> +	struct regmap_config *regmap_cfg __free(kfree) = kzalloc(sizeof(*regmap_cfg), GFP_KERNEL);
> +	if (!regmap_cfg)
> +		return -ENOMEM;
>

>  	match = of_match_node(rz_sysc_match, dev->of_node);
>  	if (!match)
>  		return -ENODEV;
>  
> +	data = match->data;
> +
>  	sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL);
>  	if (!sysc)


So this function now uses both devm_ mechanism and __free() +
kzalloc. That's quite confusing / strange. I believe this is going to
be in 6.1 only, so probably not worth fixing.

Thanks and best regards,
								Pavel
-- 
In cooperation with Nabla.

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Re: [PATCH 6.1.y-cip 03/11] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 2098 bytes --]

Hi!

> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> commit c432180a7d95081353a96fd6d5bd75b0fc8a27c3 upstream.
> 
> Not all system controller registers are accessible from Linux. Accessing
> such registers generates synchronous external abort. Populate the
> readable_reg and writeable_reg members of the regmap config to inform the
> regmap core which registers can be accessed. The list will need to be
> updated whenever new system controller functionality is exported through
> regmap.

Ok.

> @@ -18,7 +37,57 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
>  	.specific_id_mask = GENMASK(27, 0),
>  };
>  
> +static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case SYS_XSPI_MAP_STAADD_CS0:
> +	case SYS_XSPI_MAP_ENDADD_CS0:
> +	case SYS_XSPI_MAP_STAADD_CS1:
> +	case SYS_XSPI_MAP_ENDADD_CS1:
> +	case SYS_GETH0_CFG:
> +	case SYS_GETH1_CFG:
> +	case SYS_PCIE_CFG:
> +	case SYS_PCIE_MON:
> +	case SYS_PCIE_ERR_MON:
> +	case SYS_PCIE_PHY:
> +	case SYS_I2C0_CFG:
> +	case SYS_I2C1_CFG:
> +	case SYS_I2C2_CFG:
> +	case SYS_I2C3_CFG:
> +	case SYS_I3C_CFG:
> +	case SYS_USB_PWRRDY:
> +	case SYS_PCIE_RST_RSM_B:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case SYS_XSPI_MAP_STAADD_CS0:
> +	case SYS_XSPI_MAP_ENDADD_CS0:
> +	case SYS_XSPI_MAP_STAADD_CS1:
> +	case SYS_XSPI_MAP_ENDADD_CS1:
> +	case SYS_PCIE_CFG:
> +	case SYS_PCIE_PHY:
> +	case SYS_I2C0_CFG:
> +	case SYS_I2C1_CFG:
> +	case SYS_I2C2_CFG:
> +	case SYS_I2C3_CFG:
> +	case SYS_I3C_CFG:
> +	case SYS_USB_PWRRDY:
> +	case SYS_PCIE_RST_RSM_B:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}

But when register is writable, it will also always be readable, right?
So Imo readable should just do if (writable) return true, to reduce
code duplication.

Thanks and best regards,
								Pavel
-- 
In cooperation with Nabla.

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Re: [PATCH 6.1.y-cip 06/11] thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 659 bytes --]

Hi!

> +++ b/drivers/thermal/Kconfig
> @@ -373,6 +373,13 @@ config RZG3S_THERMAL
>  	  Enable this to plug the RZ/G3S thermal sensor driver into the Linux
>  	  thermal framework.
>  
> +config RZG3E_THERMAL
> +	tristate "Renesas RZ/G3E thermal driver"
> +	depends on ARCH_RENESAS || COMPILE_TEST
> +	help
> +	 Enable this to plug the RZ/G3E thermal sensor driver into the Linux
> +	 thermal framework
> +

There should really be "." at the end of sentence. Plus, there's
something wrong with indentation here, as this is indented differently
from the entry above.

Thanks and best regards,
								Pavel
-- 
In cooperation with Nabla.

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Re: [PATCH 6.1.y-cip 07/11] thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1569 bytes --]

Hi!

> From: John Madieu <john.madieu.xa@bp.renesas.com>
> 
> commit dc67521c20b701b5237ff486ae078829dc1f8fea upstream.
> 
> When applied the change commit 19d3a401a617, a conflict appeared
> resulting into a manual fix. However the new file rzg3e_thermal.c was
> not added but stayed locally in source tree and miss to be merged with
> the entire change.
> 
> Fix this by adding the file back.

Ok, so you know you made a mistake, but for -cip, it would be
better to put this before the 6/ patch. You can't undo the mistake for
mainline, but ou can do that for -cip :-).

> Fixes: 19d3a401a617 ("Add thermal driver for the Renesas RZ/G3E SoC")

>  - used devm_reset_control_get_exclusive() + reset_control_deassert() +
>    devm_add_action_or_reset() instead of
>    devm_reset_control_get_exclusive_deasserted() as the latter is not
>    available in v6.1 CIP; added rzg3e_thermal_reset_assert() action
>    function for this

Yep so... this seems to be repeat issue in Renesas patches. Are we
going to hit it again in future? If so, maybe we should introduce
devm_reset_control_get_exclusive_deasserted() to 6.1, too.

> +	/* Convert to temperature */
> +	*temp = rzg3e_thermal_code_to_temp(priv, code);
> +
> +	dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n",
> +		*temp, *temp / 1000, abs(*temp) % 1000, code);
> +

I'd expect dmesg output to be ASCII, not unicode, as it goes over
various serial lines etc. So maybe °C -> degC or just C.

Thanks and best regards,
								Pavel
-- 
In cooperation with Nabla.

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Re: [cip-dev] [PATCH 6.1.y-cip 00/11] Add RZ/V2H TSU support

[Pavel Machek]

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Hi!

> > I reviewed this series, looks good to me.
> > I can applyt this patch if there are no other comments and no issues on CI.
> >  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2293415029
> > 
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
> > 
> > Best regards,
> >   Nobuhiro
> 
> Applied and pushed, thanks.

Thank you!

For the record, I reviewed this and 6.12 version, and had some minor
comments but nothing that should prevent merge.

Best regards,
								Pavel
-- 
In cooperation with Nabla.

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