[PATCH 6.1.y-cip 0/2] ADD RZ/G3E TSU support

[PATCH 6.1.y-cip 0/2] ADD RZ/G3E TSU support

[John Madieu]

Hi,

This series adds the TSU (thermal sensor) support for Renesas RZ/G3E and
addresses an unbind issue seen with the TSU device.

Patch 1 extends the PM domain detach allowlist to include the RZ/G3E SoC
compatible, avoiding asynchronous aborts when the TSU is unbound.

Patch 2 backports the upstream RZ/G3E TSU DTSI support (TSU node, thermal zone,
and CPU cooling maps). It also adds a "syscon" fallback compatible to the
system-controller node so the TSU driver can access calibration data via
syscon_regmap_lookup_by_phandle_args().

This has been tested on an RZ/G3E SMARC platform.

Thanks,
John Madieu

John Madieu (2):
  PM: domains: Add RZ/G3E compatible to PM domain detach list
  arm64: dts: renesas: r9a09g047: Add TSU node

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 50 +++++++++++++++++++++-
 drivers/base/power/common.c                |  1 +
 2 files changed, 50 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH 6.1.y-cip 1/2] PM: domains: Add RZ/G3E compatible to PM domain detach list

[John Madieu]

Add Renesas RZ/G3E compatible string to the PM domain detach list in
dev_pm_domain_allow_detach_on_unbind_cleanup(). This avoid asynchronous
aborts when unbinding the TSU device.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 drivers/base/power/common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
index 8e002aa131f0..44c485f0c96b 100644
--- a/drivers/base/power/common.c
+++ b/drivers/base/power/common.c
@@ -245,6 +245,7 @@ bool dev_pm_domain_allow_detach_on_unbind_cleanup(void)
 		"renesas,r9a07g044", /* Renesas RZ/G2{L, LC} */
 		"renesas,r9a07g054", /* Renesas RZ/V2L */
 		"renesas,r9a08g045", /* Renesas RZ/G3S */
+		"renesas,r9a09g047", /* Renesas RZ/G3E */
 		"renesas,r9a09g057", /* Renesas RZ/V2H */
 		NULL
 	};
-- 
2.25.1

[PATCH 6.1.y-cip 2/2] arm64: dts: renesas: r9a09g047: Add TSU node

[John Madieu]

[ Upstream commit 1ad66039bef99a8e7e109f5f79c3b95f1ce8bb82 ]

Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250917170202.197929-4-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[john.madieu:
 Add "syscon" compatible fallback to system-controller node, so that
 TSU can access calibration data using syscon_regmap_lookup_by_phandle_args().
 This is mandatory prior commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes
 without a "syscon" compatible").]
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 50 +++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index c8cbe53ad4b0..bd15725f2c22 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -65,6 +65,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -75,6 +76,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -85,6 +87,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -95,6 +98,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -274,7 +278,7 @@ cpg: clock-controller@10420000 {
 		};
 
 		sys: system-controller@10430000 {
-			compatible = "renesas,r9a09g047-sys";
+			compatible = "renesas,r9a09g047-sys", "syscon";
 			reg = <0 0x10430000 0 0x10000>;
 			clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>;
 			resets = <&cpg 0x30>;
@@ -617,6 +621,19 @@ wdt3: watchdog@13000400 {
 			status = "disabled";
 		};
 
+		tsu: thermal@14002000 {
+			compatible = "renesas,r9a09g047-tsu";
+			reg = <0 0x14002000 0 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x10a>;
+			resets = <&cpg 0xf8>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x330>;
+		};
+
 		i2c0: i2c@14400400 {
 			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
 			reg = <0 0x14400400 0 0x400>;
@@ -1173,6 +1190,37 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu>;
+
+			cooling-maps {
+				map0 {
+					trip = <&target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor_crit: sensor-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.25.1

Re: [cip-dev] [PATCH 6.1.y-cip 0/2] ADD RZ/G3E TSU support

[Pavel Machek]

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Hi!

> This series adds the TSU (thermal sensor) support for Renesas RZ/G3E and
> addresses an unbind issue seen with the TSU device.
> 
> Patch 1 extends the PM domain detach allowlist to include the RZ/G3E SoC
> compatible, avoiding asynchronous aborts when the TSU is unbound.
> 
> Patch 2 backports the upstream RZ/G3E TSU DTSI support (TSU node, thermal zone,
> and CPU cooling maps). It also adds a "syscon" fallback compatible to the
> system-controller node so the TSU driver can access calibration data via
> syscon_regmap_lookup_by_phandle_args().
> 
> This has been tested on an RZ/G3E SMARC platform.

Same as 6.12, this looks okay to me.

Reviewed-by: Pavel Machek <pavel@nabladev.com>

I can apply the series if it passes testing and there are no other
comments.

Best regards,
                                                                Pavel


-- 
In cooperation with Nabla.

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RE: [cip-dev] [PATCH 6.1.y-cip 0/2] ADD RZ/G3E TSU support

[nobuhiro.iwamatsu.x90]

Hi all,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
> Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Tuesday, February 3, 2026 8:23 PM
> To: john.madieu.xa@bp.renesas.com
> Cc: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○
> ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek
> <pavel@nabladev.com>; Biju Das <biju.das.jz@bp.renesas.com>; Lad
> Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> john.madieu@gmail.com
> Subject: Re: [cip-dev] [PATCH 6.1.y-cip 0/2] ADD RZ/G3E TSU support
> 
> Hi!
> 
> > This series adds the TSU (thermal sensor) support for Renesas RZ/G3E
> > and addresses an unbind issue seen with the TSU device.
> >
> > Patch 1 extends the PM domain detach allowlist to include the RZ/G3E
> > SoC compatible, avoiding asynchronous aborts when the TSU is unbound.
> >
> > Patch 2 backports the upstream RZ/G3E TSU DTSI support (TSU node,
> > thermal zone, and CPU cooling maps). It also adds a "syscon" fallback
> > compatible to the system-controller node so the TSU driver can access
> > calibration data via syscon_regmap_lookup_by_phandle_args().
> >
> > This has been tested on an RZ/G3E SMARC platform.
> 
> Same as 6.12, this looks okay to me.
> 
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
> 

I reviewed this series. Looks good to me too.
I applied and pushed with Pavel's reviewed-by tag.

> I can apply the series if it passes testing and there are no other comments.
> 
> Best regards,
>                                                                 Pavel

Best regards,
  Nobuhiro