Re: [PATCH 6.1.y-cip 18/25] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

[Pavel Machek <pavel@nabladev.com>]

[-- Attachment #1: Type: text/plain, Size: 1642 bytes --]

Hi!

> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> commit e2944dc6587f39c3eefb15ee607e700314230a0b upstream.
> 
> Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
> `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
> supported display modes.
> 
> On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
> possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs,
> function pointers are introduced.
> 
> Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock
> configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke
> `dphy_mode_clk_check` for mode validation.
> 
> This change ensures proper operation across different SoC variants
> by allowing fine-grained control over clock configuration and mode
> validation.

> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -276,12 +280,39 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi)
>  	reset_control_assert(dsi->rstc);
>  }
>  
> +static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
> +				u64 *hsfreq_millihz)
> +{
> +	unsigned long vclk_rate;
> +	unsigned int bpp;
> +
> +	clk_set_rate(dsi->vclk, mode_freq * KILO);
> +	vclk_rate = clk_get_rate(dsi->vclk);
> +	if (vclk_rate != mode_freq * KILO)
> +		dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
> +			mode_freq * KILO, vclk_rate);

I believe what the message is trying to say is there's mismatch
between requested and actual rate.

In such case, "-- mismatch" would make it more clear.

Thanks,
								Pavel

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]