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From: Pavel Machek <pavel@nabladev.com>
To: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Cc: cip-dev@lists.cip-project.org, pavel@nabladev.com,
	nobuhiro.iwamatsu.x90@mail.toshiba
Subject: Re: [PATCH 6.1.y-cip 20/25] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC
Date: Fri, 27 Feb 2026 11:05:10 +0100	[thread overview]
Message-ID: <aaFsVjmlSMUJlAkN@duo.ucw.cz> (raw)
In-Reply-To: <20260225121003.129467-21-ovidiu.panait.rb@renesas.com>

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Hi!

> Add MIPI DSI support for the Renesas RZ/V2H(P) SoC. Compared to the
> RZ/G2L family, the RZ/V2H(P) requires dedicated D-PHY PLL programming,
> different clock configuration, and additional timing parameter handling.
> The driver introduces lookup tables and helpers for D-PHY timings
> (TCLK*, THS*, TLPX, and ULPS exit) as specified in the RZ/V2H(P) hardware
> manual. ULPS exit timing depends on the LPCLK rate and is now handled
> explicitly.
> 
> The implementation also adds support for 16 bpp RGB format, updates the
> clock setup path to use the RZ/V2H PLL divider limits, and provides new
> .dphy_init, .dphy_conf_clks, and .dphy_startup_late_init callbacks to
> match the RZ/V2H sequence.
> 
> With these changes, the RZ/V2H(P) can operate the MIPI DSI interface in
> compliance with its hardware specification while retaining support for
> existing RZ/G2L platforms.

> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c


> +static const u8 thsexitctl[] = {
> +	15, 23, 31, 39, 47, 55, 63, 71, 79, 87,
> +	95, 103, 111, 119, 127, 135, 143, 150,
> +};

Some _'s in the control names would make these more clear. I believe
it is ths_exit_ctl, but... there are more confusing ways to parse this.

> +/**
> + * rzv2h_dphy_find_timings_val - Find timing parameter value from lookup tables
> + * @freq: Input frequency in Hz
> + * @index: Index to select timing parameter table (see enum rzv2h_dsi_timing_idx)
> + *
> + * Selects the timing table for the requested parameter, finds the
> + * frequency range entry and returns the register value to program:
> + *
> + *   register_value = timings->base_value + table_index
> + *
> + * Note: frequency table entries are stored as small integers (units of 10):

This should probably say "units of of 10MHz", if I'm reading that correctly.

> +
> +static const u8 rzv2h_cpg_div_table[] = {
> +	2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32,
> +};

Ok, so this is table of even numbers. Other tables seem to have kind
of regular, too. Documenting how the tables were created would not be
bad.

Thanks and best regards,
								Pavel

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  reply	other threads:[~2026-02-27 10:05 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-25 12:09 [PATCH 6.1.y-cip 00/25] Add RZ/V2H display support Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 01/25] dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 02/25] dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 03/25] media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P) Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 04/25] media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoC Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 05/25] dt-bindings: display: renesas,rzg2l-du: Add support for " Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 06/25] clk: renesas: rzv2h: Add instance field to struct pll Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 07/25] clk: renesas: rzv2h: Use GENMASK for PLL fields Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 08/25] clk: renesas: rzv2h: Add support for DSI clocks Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 09/25] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 10/25] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 11/25] drm: renesas: rz-du: mipi_dsi: Use VCLK for " Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 12/25] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 13/25] drm: renesas: rz-du: mipi_dsi: Add OF data support Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 14/25] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P) Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 15/25] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 16/25] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 17/25] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 18/25] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Ovidiu Panait
2026-02-27  9:57   ` Pavel Machek
2026-02-25 12:09 ` [PATCH 6.1.y-cip 19/25] drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support Ovidiu Panait
2026-02-25 12:09 ` [PATCH 6.1.y-cip 20/25] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Ovidiu Panait
2026-02-27 10:05   ` Pavel Machek [this message]
2026-02-25 12:09 ` [PATCH 6.1.y-cip 21/25] drm: renesas: rz-du: " Ovidiu Panait
2026-02-25 12:10 ` [PATCH 6.1.y-cip 22/25] drm: renesas: rz-du: Drop ARCH_RZG2L dependency Ovidiu Panait
2026-02-25 12:10 ` [PATCH 6.1.y-cip 23/25] arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodes Ovidiu Panait
2026-02-25 12:10 ` [PATCH 6.1.y-cip 24/25] arm64: dts: renesas: r9a09g057: Add DU and DSI nodes Ovidiu Panait
2026-02-25 12:10 ` [PATCH 6.1.y-cip 25/25] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable DU and DSI Ovidiu Panait
2026-02-27 10:08 ` [PATCH 6.1.y-cip 00/25] Add RZ/V2H display support Pavel Machek
2026-03-07 10:37 ` Pavel Machek

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