* [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support
@ 2026-03-10 16:00 Ovidiu Panait
2026-03-10 16:00 ` [PATCH 6.12.y-cip 1/5] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC Ovidiu Panait
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
Hi,
This series adds Interrupt Controller Unit (ICU) support for the
Renesas RZ/V2N SoC.
Patches were cherry-picked from mainline kernel.
Note: This series depends on:
https://lore.kernel.org/cip-dev/20260305153725.19821-1-ovidiu.panait.rb@renesas.com/
Best regards,
Ovidiu
Lad Prabhakar (5):
dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N
SoC
clk: renesas: r9a09g056: Add entries for ICU
irqchip/renesas-rzv2h: Add support for RZ/V2N SoC
arm64: dts: renesas: r9a09g056: Add ICU node
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button
support
.../renesas,rzv2h-icu.yaml | 1 +
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 92 +++++++++++++++++++
.../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 13 +++
drivers/clk/renesas/r9a09g056-cpg.c | 3 +
drivers/irqchip/irq-renesas-rzv2h.c | 1 +
5 files changed, 110 insertions(+)
--
2.51.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 6.12.y-cip 1/5] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait @ 2026-03-10 16:00 ` Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 2/5] clk: renesas: r9a09g056: Add entries for ICU Ovidiu Panait ` (4 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw) To: cip-dev, pavel, nobuhiro.iwamatsu.x90 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit c71869c61d7cf2070421cdcc4dd64c4c860df49d upstream. Document the Interrupt Control Unit (ICU) used on the Renesas RZ/V2N SoC. Although the ICU closely matches the design found on the RZ/V2H(P) family, it differs in its register layout, particularly in the reduced set of ECCRAM related registers. These variations require a distinct compatible string so that software can correctly match and handle the RZ/V2N implementation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251127162447.320971-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index 3f99c8645767..cb244b8f5e1c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g056-icu # RZ/V2N - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': -- 2.51.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6.12.y-cip 2/5] clk: renesas: r9a09g056: Add entries for ICU 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 1/5] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC Ovidiu Panait @ 2026-03-10 16:00 ` Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 3/5] irqchip/renesas-rzv2h: Add support for RZ/V2N SoC Ovidiu Panait ` (3 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw) To: cip-dev, pavel, nobuhiro.iwamatsu.x90 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit 94cdeca6a17a3e2ba617c8a03e17d989de005a20 upstream. Add clock and reset entries for the ICU IP block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125221420.288809-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> --- drivers/clk/renesas/r9a09g056-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c index 73c63cef8a99..b7d66148b42c 100644 --- a/drivers/clk/renesas/r9a09g056-cpg.c +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -214,6 +214,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, @@ -354,6 +356,7 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g056_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ -- 2.51.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6.12.y-cip 3/5] irqchip/renesas-rzv2h: Add support for RZ/V2N SoC 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 1/5] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 2/5] clk: renesas: r9a09g056: Add entries for ICU Ovidiu Panait @ 2026-03-10 16:00 ` Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g056: Add ICU node Ovidiu Panait ` (2 subsequent siblings) 5 siblings, 0 replies; 8+ messages in thread From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw) To: cip-dev, pavel, nobuhiro.iwamatsu.x90 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit 8d4c354bef3cc438db93f362e4657b317db03392 upstream. Add support for the RZ/V2N Interrupt Control Unit (ICU) by introducing a dedicated compatible string in the irqchip driver. While the RZ/V2N ICU differs from the RZ/V2H(P) version in its register layout primarily due to a reduced set of ECCRAM related registers the irqchip driver does not currently access these registers. As a result, the RZ/V2N ICU can be safely handled by rzv2h_icu_probe for now, but it still requires a distinct compatible so that future changes can differentiate the SoCs when needed. [ tglx: Fixed up the made up subject prefix ] Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251127162447.320971-3-prabhakar.mahadev-lad.rj@bp.renesas.com [OP: used rzv2h_icu_init instead of rzv2h_icu_probe in IRQCHIP_MATCH()] Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> --- drivers/irqchip/irq-renesas-rzv2h.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 766adccf11dc..b8dc29fc1198 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -632,6 +632,7 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init) +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_init) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>"); -- 2.51.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g056: Add ICU node 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait ` (2 preceding siblings ...) 2026-03-10 16:00 ` [PATCH 6.12.y-cip 3/5] irqchip/renesas-rzv2h: Add support for RZ/V2N SoC Ovidiu Panait @ 2026-03-10 16:00 ` Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 5/5] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support Ovidiu Panait 2026-03-11 10:34 ` [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Pavel Machek 5 siblings, 0 replies; 8+ messages in thread From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw) To: cip-dev, pavel, nobuhiro.iwamatsu.x90 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit b449dbc0bb0301277a6de444901a7122214c090d upstream. Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 96765312398c..cfd52a3158ac 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -178,12 +178,104 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g056-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g056-pinctrl"; reg = <0 0x10410000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; -- 2.51.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6.12.y-cip 5/5] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait ` (3 preceding siblings ...) 2026-03-10 16:00 ` [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g056: Add ICU node Ovidiu Panait @ 2026-03-10 16:00 ` Ovidiu Panait 2026-03-11 10:34 ` [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Pavel Machek 5 siblings, 0 replies; 8+ messages in thread From: Ovidiu Panait @ 2026-03-10 16:00 UTC (permalink / raw) To: cip-dev, pavel, nobuhiro.iwamatsu.x90 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> commit 41e60d92c88c0085511b38077dad2939bf63ddfc upstream. Add support for the NMI connected user pushbutton on the RZ/V2N EVK. The button is wired to the SoC NMI input and can be used to wake the system from low-power states. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251125224533.294235-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 2846a1b23cd7..e7bb4334ca47 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include "r9a09g056.dtsi" / { @@ -44,6 +45,18 @@ hdmi_con_out: endpoint { }; }; + keys: keys { + compatible = "gpio-keys"; + + key-wakeup { + interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_WAKEUP>; + label = "NMI_SW"; + debounce-interval = <20>; + wakeup-source; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ -- 2.51.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait ` (4 preceding siblings ...) 2026-03-10 16:00 ` [PATCH 6.12.y-cip 5/5] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support Ovidiu Panait @ 2026-03-11 10:34 ` Pavel Machek 2026-03-12 3:34 ` [cip-dev] " nobuhiro.iwamatsu.x90 5 siblings, 1 reply; 8+ messages in thread From: Pavel Machek @ 2026-03-11 10:34 UTC (permalink / raw) To: Ovidiu Panait; +Cc: cip-dev, pavel, nobuhiro.iwamatsu.x90 [-- Attachment #1: Type: text/plain, Size: 524 bytes --] Hi! > This series adds Interrupt Controller Unit (ICU) support for the > Renesas RZ/V2N SoC. > > Patches were cherry-picked from mainline kernel. > > Note: This series depends on: > https://lore.kernel.org/cip-dev/20260305153725.19821-1-ovidiu.panait.rb@renesas.com/ This looks okay to me. Reviewed-by: Pavel Machek <pavel@nabladev.com> I can apply the series if it passes testing and there are no other comments. Best regards, Pavel [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 195 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [cip-dev] [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support 2026-03-11 10:34 ` [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Pavel Machek @ 2026-03-12 3:34 ` nobuhiro.iwamatsu.x90 0 siblings, 0 replies; 8+ messages in thread From: nobuhiro.iwamatsu.x90 @ 2026-03-12 3:34 UTC (permalink / raw) To: pavel, ovidiu.panait.rb; +Cc: cip-dev Hi all, > -----Original Message----- > From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org > Sent: Wednesday, March 11, 2026 7:34 PM > To: Ovidiu Panait <ovidiu.panait.rb@renesas.com> > Cc: cip-dev@lists.cip-project.org; pavel@nabladev.com; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ) > <nobuhiro.iwamatsu.x90@mail.toshiba> > Subject: Re: [cip-dev] [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support > > Hi! > > > This series adds Interrupt Controller Unit (ICU) support for the > > Renesas RZ/V2N SoC. > > > > Patches were cherry-picked from mainline kernel. > > > > Note: This series depends on: > > https://lore.kernel.org/cip-dev/20260305153725.19821-1-ovidiu.panait.r > > b@renesas.com/ > > This looks okay to me. > > Reviewed-by: Pavel Machek <pavel@nabladev.com> > > I can apply the series if it passes testing and there are no other comments. I reviewed this series, looks good to me too. I will apply with Pavel's Reviewed-by tag, and push. > > Best regards, > Pavel Best regards, Nobuhiro ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-03-12 3:34 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-03-10 16:00 [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 1/5] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 2/5] clk: renesas: r9a09g056: Add entries for ICU Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 3/5] irqchip/renesas-rzv2h: Add support for RZ/V2N SoC Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 4/5] arm64: dts: renesas: r9a09g056: Add ICU node Ovidiu Panait 2026-03-10 16:00 ` [PATCH 6.12.y-cip 5/5] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support Ovidiu Panait 2026-03-11 10:34 ` [PATCH 6.12.y-cip 0/5] Add RZ/V2N Interrupt Controller Unit (ICU) support Pavel Machek 2026-03-12 3:34 ` [cip-dev] " nobuhiro.iwamatsu.x90
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