* [PATCH 6.12.y-cip 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
` (10 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit a24cd110e664396061b0a72930734bf419bf88c4 ]
Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250909180803.140939-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..f165df8a6f5a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
#define R9A09G047_SPI_CLK_SPI 9
#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
+#define R9A09G047_USB3_0_REF_ALT_CLK_P 12
+#define R9A09G047_USB3_0_CLKCORE 13
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 03/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
` (9 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 82e0aa95ec8cec76bec23146ad8effb5a09e6e92 ]
Add USB3.0 clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250909180803.140939-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a09g047-cpg.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index c791b3d47f16..b112e436433a 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -16,7 +16,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
- LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
+ LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
/* External Input Clocks */
CLK_AUDIO_EXTAL,
@@ -187,6 +187,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
CLK_PLLETH_DIV_125_FIX, 1, 1),
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
CLK_PLLETH_DIV_125_FIX, 1, 1),
+ DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
+ DEF_FIXED("usb3_0_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
};
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
@@ -378,6 +380,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
BUS_MSTOP(8, BIT(4))),
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
BUS_MSTOP(8, BIT(4))),
+ DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
+ BUS_MSTOP(7, BIT(12))),
+ DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
+ BUS_MSTOP(7, BIT(14))),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
BUS_MSTOP(8, BIT(5)), 1),
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -470,6 +476,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
+ DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 03/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 04/11] usb: host: xhci-rcar: Move R-Car reg definitions Biju
` (8 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit dd0d2618e3f815a030622599e540d3be1964a888 ]
Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
Revision 1.0.
- Supports 1 downstream USB receptacles
- Number of SSP Gen2 or SS ports: 1
- Number of HS or FS or LS ports: 1
- Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
- Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
these split-transactions.
- Supports Power Control and Over Current Detection.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250916150255.4231-4-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/usb/renesas,rzg3e-xhci.yaml | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
new file mode 100644
index 000000000000..98260f9fb442
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.2 Gen2 Host controller
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-xhci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Logical OR of all interrupt signals.
+ - description: System management interrupt
+ - description: Host system error interrupt
+ - description: Power management event interrupt
+ - description: xHC interrupt
+
+ interrupt-names:
+ items:
+ - const: all
+ - const: smi
+ - const: hse
+ - const: pme
+ - const: xhc
+
+ clocks:
+ maxItems: 1
+
+ phys:
+ maxItems: 2
+
+ phy-names:
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+ - phys
+ - phy-names
+
+allOf:
+ - $ref: usb-xhci.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb@15850000 {
+ compatible = "renesas,r9a09g047-xhci";
+ reg = <0x15850000 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 04/11] usb: host: xhci-rcar: Move R-Car reg definitions
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (2 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 03/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 05/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv Biju
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit f7acd12eba05fb9e7dba3222e2aeca5f49d38b3a ]
Move xhci-rcar reg definitions to a header file for the preparation of adding
support for RZ/G3E XHCI that has different register definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250916150255.4231-5-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/xhci-rcar-regs.h | 49 +++++++++++++++++++++++++++++++
drivers/usb/host/xhci-rcar.c | 45 +---------------------------
2 files changed, 50 insertions(+), 44 deletions(-)
create mode 100644 drivers/usb/host/xhci-rcar-regs.h
diff --git a/drivers/usb/host/xhci-rcar-regs.h b/drivers/usb/host/xhci-rcar-regs.h
new file mode 100644
index 000000000000..5ecbda858be0
--- /dev/null
+++ b/drivers/usb/host/xhci-rcar-regs.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __XHCI_RCAR_H
+#define __XHCI_RCAR_H
+
+/*** Register Offset ***/
+#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
+#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
+#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
+#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
+
+#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
+#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
+#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
+#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
+#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
+#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
+
+/*** Register Settings ***/
+/* AXI Host Control Status */
+#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
+#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
+#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
+ RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
+
+/* Interrupt Enable */
+#define RCAR_USB3_INT_XHC_ENA 0x00000001
+#define RCAR_USB3_INT_PME_ENA 0x00000002
+#define RCAR_USB3_INT_HSE_ENA 0x00000004
+#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
+ RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
+
+/* FW Download Control & Status */
+#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
+#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
+#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
+
+/* LCLK Select */
+#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
+
+/* USB3.0 Configuration */
+#define RCAR_USB3_CONF1_VAL 0x00030204
+#define RCAR_USB3_CONF2_VAL 0x00030300
+#define RCAR_USB3_CONF3_VAL 0x13802007
+
+/* USB3.0 Polarity */
+#define RCAR_USB3_RX_POL_VAL BIT(21)
+#define RCAR_USB3_TX_POL_VAL BIT(4)
+
+#endif /* __XHCI_RCAR_H */
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index 8b357647728c..b5099d2e2e65 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -14,6 +14,7 @@
#include "xhci.h"
#include "xhci-plat.h"
+#include "xhci-rcar-regs.h"
#include "xhci-rzv2m.h"
#define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
@@ -29,50 +30,6 @@
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
-/*** Register Offset ***/
-#define RCAR_USB3_AXH_STA 0x104 /* AXI Host Control Status */
-#define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
-#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
-#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
-
-#define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
-#define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
-#define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
-#define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
-#define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
-#define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
-
-/*** Register Settings ***/
-/* AXI Host Control Status */
-#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE 0x00010000
-#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE 0x00000001
-#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
- RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
-
-/* Interrupt Enable */
-#define RCAR_USB3_INT_XHC_ENA 0x00000001
-#define RCAR_USB3_INT_PME_ENA 0x00000002
-#define RCAR_USB3_INT_HSE_ENA 0x00000004
-#define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
- RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
-
-/* FW Download Control & Status */
-#define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
-#define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
-#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
-
-/* LCLK Select */
-#define RCAR_USB3_LCLK_ENA_VAL 0x01030001
-
-/* USB3.0 Configuration */
-#define RCAR_USB3_CONF1_VAL 0x00030204
-#define RCAR_USB3_CONF2_VAL 0x00030300
-#define RCAR_USB3_CONF3_VAL 0x13802007
-
-/* USB3.0 Polarity */
-#define RCAR_USB3_RX_POL_VAL BIT(21)
-#define RCAR_USB3_TX_POL_VAL BIT(4)
-
static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
{
/* LCLK Select */
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 05/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (3 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 04/11] usb: host: xhci-rcar: Move R-Car reg definitions Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 06/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support Biju
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 2ef16e4eb41fe711479d92805e4b9e430c7bbefd ]
Some SoCs (eg Renesas RZ/G3E SoC) have special sequence after
xhci_resume, add .post_resume_quick for it.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250916150255.4231-6-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/xhci-plat.c | 14 ++++++++++++++
drivers/usb/host/xhci-plat.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 448656d68e49..48e0463ee194 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -74,6 +74,16 @@ static int xhci_priv_resume_quirk(struct usb_hcd *hcd)
return priv->resume_quirk(hcd);
}
+static int xhci_priv_post_resume_quirk(struct usb_hcd *hcd)
+{
+ struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
+
+ if (!priv->post_resume_quirk)
+ return 0;
+
+ return priv->post_resume_quirk(hcd);
+}
+
static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
{
struct xhci_plat_priv *priv = xhci_to_priv(xhci);
@@ -505,6 +515,10 @@ static int xhci_plat_resume_common(struct device *dev, struct pm_message pmsg)
if (ret)
goto disable_clks;
+ ret = xhci_priv_post_resume_quirk(hcd);
+ if (ret)
+ goto disable_clks;
+
pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
diff --git a/drivers/usb/host/xhci-plat.h b/drivers/usb/host/xhci-plat.h
index 6475130eac4b..8c904b0fe555 100644
--- a/drivers/usb/host/xhci-plat.h
+++ b/drivers/usb/host/xhci-plat.h
@@ -19,6 +19,7 @@ struct xhci_plat_priv {
int (*init_quirk)(struct usb_hcd *);
int (*suspend_quirk)(struct usb_hcd *);
int (*resume_quirk)(struct usb_hcd *);
+ int (*post_resume_quirk)(struct usb_hcd *);
};
#define hcd_to_xhci_priv(h) ((struct xhci_plat_priv *)hcd_to_xhci(h)->priv)
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 06/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (4 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 05/11] usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 07/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY Biju
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 5db5025d32e5b0b4c13198b5570f33d92ae941d3 ]
The USB3.2 Gen2 Host controller (a.k.a USB3HOST), IP found on the RZ/G3E
SoC is similar to R-Car XHCI, but it doesn't require any firmware.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250916150255.4231-7-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/xhci-rcar.c | 55 ++++++++++++++++++++++++++++++
drivers/usb/host/xhci-rzg3e-regs.h | 12 +++++++
3 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/host/xhci-rzg3e-regs.h
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d011d6c753ed..0169b62ee412 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -93,7 +93,7 @@ config USB_XHCI_RCAR
default ARCH_RENESAS
help
Say 'Y' to enable the support for the xHCI host controller
- found in Renesas R-Car ARM SoCs.
+ found in Renesas R-Car and RZ/G3E alike ARM SoCs.
config USB_XHCI_RZV2M
bool "xHCI support for Renesas RZ/V2M SoC"
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
index b5099d2e2e65..87c50f6bca6d 100644
--- a/drivers/usb/host/xhci-rcar.c
+++ b/drivers/usb/host/xhci-rcar.c
@@ -11,10 +11,12 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/usb/phy.h>
+#include <linux/reset.h>
#include "xhci.h"
#include "xhci-plat.h"
#include "xhci-rcar-regs.h"
+#include "xhci-rzg3e-regs.h"
#include "xhci-rzv2m.h"
#define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
@@ -67,6 +69,48 @@ static void xhci_rcar_start(struct usb_hcd *hcd)
}
}
+static void xhci_rzg3e_start(struct usb_hcd *hcd)
+{
+ u32 int_en;
+
+ if (hcd->regs) {
+ /* Update the controller initial setting */
+ writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(0));
+ writel(0x00160200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(1));
+ writel(0x03150000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(2));
+ writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(3));
+ writel(0x00180000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(4));
+
+ /* Interrupt Enable */
+ int_en = readl(hcd->regs + RZG3E_USB3_HOST_INTEN);
+ int_en |= RZG3E_USB3_HOST_INTEN_ENA;
+ writel(int_en, hcd->regs + RZG3E_USB3_HOST_INTEN);
+ }
+}
+
+static int xhci_rzg3e_resume(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ return reset_control_deassert(xhci->reset);
+}
+
+static int xhci_rzg3e_post_resume(struct usb_hcd *hcd)
+{
+ xhci_rzg3e_start(hcd);
+
+ return 0;
+}
+
+static int xhci_rzg3e_suspend(struct usb_hcd *hcd)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ reset_control_assert(xhci->reset);
+
+ return 0;
+}
+
static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
{
struct device *dev = hcd->self.controller;
@@ -190,6 +234,14 @@ static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
.plat_start = xhci_rzv2m_start,
};
+static const struct xhci_plat_priv xhci_plat_renesas_rzg3e = {
+ .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_RESET_ON_RESUME | XHCI_SUSPEND_RESUME_CLKS,
+ .plat_start = xhci_rzg3e_start,
+ .suspend_quirk = xhci_rzg3e_suspend,
+ .resume_quirk = xhci_rzg3e_resume,
+ .post_resume_quirk = xhci_rzg3e_post_resume,
+};
+
static const struct of_device_id usb_xhci_of_match[] = {
{
.compatible = "renesas,xhci-r8a7790",
@@ -206,6 +258,9 @@ static const struct of_device_id usb_xhci_of_match[] = {
}, {
.compatible = "renesas,xhci-r8a7796",
.data = &xhci_plat_renesas_rcar_gen3,
+ }, {
+ .compatible = "renesas,r9a09g047-xhci",
+ .data = &xhci_plat_renesas_rzg3e,
}, {
.compatible = "renesas,rcar-gen2-xhci",
.data = &xhci_plat_renesas_rcar_gen2,
diff --git a/drivers/usb/host/xhci-rzg3e-regs.h b/drivers/usb/host/xhci-rzg3e-regs.h
new file mode 100644
index 000000000000..7a244a47b882
--- /dev/null
+++ b/drivers/usb/host/xhci-rzg3e-regs.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __XHCI_RZG3E_H
+#define __XHCI_RZG3E_H
+
+#define RZG3E_USB3_HOST_INTEN 0x1044 /* Interrupt Enable */
+#define RZG3E_USB3_HOST_U3P0PIPESC(x) (0x10c0 + (x) * 4) /* PIPE Status and Control Register */
+
+#define RZG3E_USB3_HOST_INTEN_XHC BIT(0)
+#define RZG3E_USB3_HOST_INTEN_HSE BIT(2)
+#define RZG3E_USB3_HOST_INTEN_ENA (RZG3E_USB3_HOST_INTEN_XHC | RZG3E_USB3_HOST_INTEN_HSE)
+
+#endif /* __XHCI_RZG3E_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 07/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (5 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 06/11] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
` (4 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 4f816512aaa1fa3b74df7473ef771ebef511255e ]
Document Renesas RZ/G3E USB3.0 PHY. This IP is connected between
USB3HOST and PHY module. The main functions of the module are
as follows:
- Reset control
- Control of PHY input pins
- Monitoring of PHY output pins
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251029084037.108610-2-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/phy/renesas,rzg3e-usb3-phy.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
new file mode 100644
index 000000000000..b86dc7a291a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.0 PHY
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: USB 2.0 PHY reference clock
+ - description: USB 3.0 PHY reference clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: core
+ - const: ref_alt_clk_p
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+ usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0x15870000 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (6 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 07/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY Biju
@ 2026-03-12 15:35 ` Biju
2026-03-18 10:02 ` Pavel Machek
2026-03-12 15:35 ` [PATCH 6.12.y-cip 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Biju
` (3 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit ee5f1a3f90a4720f89fd1e250fa6754470da1510 ]
Add Renesas RZ/G3E USB3.0 PHY driver. This module is connected
between USB3 Host and PHY module. The main functions of this
module are:
1) Reset control
2) Control of PHY input pins
3) Monitoring of PHY output pins
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20251029084037.108610-3-biju.das.jz@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/phy/renesas/Kconfig | 7 +
drivers/phy/renesas/Makefile | 1 +
drivers/phy/renesas/phy-rzg3e-usb3.c | 259 +++++++++++++++++++++++++++
3 files changed, 267 insertions(+)
create mode 100644 drivers/phy/renesas/phy-rzg3e-usb3.c
diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig
index e342eef0640b..16211072098e 100644
--- a/drivers/phy/renesas/Kconfig
+++ b/drivers/phy/renesas/Kconfig
@@ -40,3 +40,10 @@ config PHY_RCAR_GEN3_USB3
select GENERIC_PHY
help
Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
+
+config PHY_RZ_G3E_USB3
+ tristate "Renesas RZ/G3E USB 3.0 PHY driver"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Support for USB 3.0 PHY found on Renesas RZ/G3E SoCs.
diff --git a/drivers/phy/renesas/Makefile b/drivers/phy/renesas/Makefile
index 8896d1919faa..0e98083f2f0c 100644
--- a/drivers/phy/renesas/Makefile
+++ b/drivers/phy/renesas/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
+obj-$(CONFIG_PHY_RZ_G3E_USB3) += phy-rzg3e-usb3.o
diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c b/drivers/phy/renesas/phy-rzg3e-usb3.c
new file mode 100644
index 000000000000..6b3453ea0004
--- /dev/null
+++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G3E USB3.0 PHY driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#define USB3_TEST_RESET 0x0000
+#define USB3_TEST_UTMICTRL2 0x0b04
+#define USB3_TEST_PRMCTRL5_R 0x0c10
+#define USB3_TEST_PRMCTRL6_R 0x0c14
+
+#define USB3_TEST_RSTCTRL 0x1000
+#define USB3_TEST_CLKCTRL 0x1004
+#define USB3_TEST_RAMCTRL 0x100c
+#define USB3_TEST_CREGCTRL 0x1010
+#define USB3_TEST_LANECONFIG0 0x1030
+
+#define USB3_TEST_RESET_PORTRESET0_CTRL BIT(9)
+#define USB3_TEST_RESET_SIDDQ BIT(3)
+#define USB3_TEST_RESET_PHY_RESET BIT(2)
+#define USB3_TEST_RESET_PORTRESET0 BIT(1)
+#define USB3_TEST_RESET_RELEASE_OVERRIDE (0)
+
+#define USB3_TEST_UTMICTRL2_CTRL_MASK GENMASK(9, 8)
+#define USB3_TEST_UTMICTRL2_MODE_MASK GENMASK(1, 0)
+
+#define USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK GENMASK(2, 1)
+
+#define USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK GENMASK(2, 0)
+
+#define USB3_TEST_RSTCTRL_HARDRESET_ODEN BIT(9)
+#define USB3_TEST_RSTCTRL_PIPERESET_ODEN BIT(8)
+#define USB3_TEST_RSTCTRL_HARDRESET BIT(1)
+#define USB3_TEST_RSTCTRL_PIPERESET BIT(0)
+#define USB3_TEST_RSTCTRL_ASSERT \
+ (USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN | \
+ USB3_TEST_RSTCTRL_HARDRESET | USB3_TEST_RSTCTRL_PIPERESET)
+#define USB3_TEST_RSTCTRL_RELEASE_HARDRESET \
+ (USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN | \
+ USB3_TEST_RSTCTRL_PIPERESET)
+#define USB3_TEST_RSTCTRL_DEASSERT \
+ (USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN)
+#define USB3_TEST_RSTCTRL_RELEASE_OVERRIDE (0)
+
+#define USB3_TEST_CLKCTRL_MPLLA_SSC_EN BIT(2)
+
+#define USB3_TEST_RAMCTRL_SRAM_INIT_DONE BIT(2)
+#define USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE BIT(0)
+
+#define USB3_TEST_CREGCTRL_PARA_SEL BIT(8)
+
+#define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
+
+struct rz_usb3 {
+ void __iomem *base;
+ struct reset_control *rstc;
+ bool skip_reinit;
+};
+
+static void rzg3e_phy_usb2test_phy_init(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + USB3_TEST_UTMICTRL2);
+ val |= USB3_TEST_UTMICTRL2_CTRL_MASK | USB3_TEST_UTMICTRL2_MODE_MASK;
+ writel(val, base + USB3_TEST_UTMICTRL2);
+
+ val = readl(base + USB3_TEST_PRMCTRL5_R);
+ val &= ~USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK;
+ val |= FIELD_PREP(USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK, 2);
+ writel(val, base + USB3_TEST_PRMCTRL5_R);
+
+ val = readl(base + USB3_TEST_PRMCTRL6_R);
+ val &= ~USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK;
+ val |= FIELD_PREP(USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK, 7);
+ writel(val, base + USB3_TEST_PRMCTRL6_R);
+
+ val = readl(base + USB3_TEST_RESET);
+ val &= ~USB3_TEST_RESET_SIDDQ;
+ val |= USB3_TEST_RESET_PORTRESET0_CTRL | USB3_TEST_RESET_PHY_RESET |
+ USB3_TEST_RESET_PORTRESET0;
+ writel(val, base + USB3_TEST_RESET);
+ fsleep(10);
+
+ val &= ~(USB3_TEST_RESET_PHY_RESET | USB3_TEST_RESET_PORTRESET0);
+ writel(val, base + USB3_TEST_RESET);
+ fsleep(10);
+
+ val = readl(base + USB3_TEST_UTMICTRL2);
+ val &= ~USB3_TEST_UTMICTRL2_CTRL_MASK;
+ writel(val, base + USB3_TEST_UTMICTRL2);
+
+ writel(USB3_TEST_RESET_RELEASE_OVERRIDE, base + USB3_TEST_RESET);
+}
+
+static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
+{
+ int ret;
+ u32 val;
+
+ writel(USB3_TEST_CREGCTRL_PARA_SEL, base + USB3_TEST_CREGCTRL);
+ writel(USB3_TEST_RSTCTRL_ASSERT, base + USB3_TEST_RSTCTRL);
+ fsleep(20);
+
+ writel(USB3_TEST_CLKCTRL_MPLLA_SSC_EN, base + USB3_TEST_CLKCTRL);
+ writel(USB3_TEST_LANECONFIG0_DEFAULT, base + USB3_TEST_LANECONFIG0);
+ writel(USB3_TEST_RSTCTRL_RELEASE_HARDRESET, base + USB3_TEST_RSTCTRL);
+
+ ret = readl_poll_timeout_atomic(base + USB3_TEST_RAMCTRL, val,
+ val & USB3_TEST_RAMCTRL_SRAM_INIT_DONE, 1, 10000);
+ if (ret)
+ return ret;
+
+ writel(USB3_TEST_RSTCTRL_DEASSERT, base + USB3_TEST_RSTCTRL);
+ writel(USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE, base + USB3_TEST_RAMCTRL);
+ writel(USB3_TEST_RSTCTRL_RELEASE_OVERRIDE, base + USB3_TEST_RSTCTRL);
+
+ return 0;
+}
+
+static int rzg3e_phy_usb3_init_helper(void __iomem *base)
+{
+ rzg3e_phy_usb2test_phy_init(base);
+
+ return rzg3e_phy_usb3test_phy_init(base);
+}
+
+static int rzg3e_phy_usb3_init(struct phy *p)
+{
+ struct rz_usb3 *r = phy_get_drvdata(p);
+ int ret = 0;
+
+ if (!r->skip_reinit)
+ ret = rzg3e_phy_usb3_init_helper(r->base);
+
+ return ret;
+}
+
+static const struct phy_ops rzg3e_phy_usb3_ops = {
+ .init = rzg3e_phy_usb3_init,
+ .owner = THIS_MODULE,
+};
+
+static int rzg3e_phy_usb3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *provider;
+ struct rz_usb3 *r;
+ struct phy *phy;
+ int ret;
+
+ r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
+ if (!r)
+ return -ENOMEM;
+
+ r->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(r->base))
+ return PTR_ERR(r->base);
+
+ r->rstc = devm_reset_control_get_shared_deasserted(dev, NULL);
+ if (IS_ERR(r->rstc))
+ return dev_err_probe(dev, PTR_ERR(r->rstc), "failed to get deasserted reset\n");
+
+ /*
+ * devm_phy_create() will call pm_runtime_enable(&phy->dev);
+ * And then, phy-core will manage runtime pm for this device.
+ */
+ ret = devm_pm_runtime_enable(dev);
+ if (ret < 0)
+ return ret;
+
+ phy = devm_phy_create(dev, NULL, &rzg3e_phy_usb3_ops);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy), "failed to create USB3 PHY\n");
+
+ platform_set_drvdata(pdev, r);
+ phy_set_drvdata(phy, r);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider), "failed to register PHY provider\n");
+
+ return 0;
+}
+
+static int rzg3e_phy_usb3_suspend(struct device *dev)
+{
+ struct rz_usb3 *r = dev_get_drvdata(dev);
+
+ pm_runtime_put(dev);
+ reset_control_assert(r->rstc);
+ r->skip_reinit = false;
+
+ return 0;
+}
+
+static int rzg3e_phy_usb3_resume(struct device *dev)
+{
+ struct rz_usb3 *r = dev_get_drvdata(dev);
+ int ret;
+
+ ret = reset_control_deassert(r->rstc);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ goto reset_assert;
+
+ ret = rzg3e_phy_usb3_init_helper(r->base);
+ if (ret)
+ goto pm_put;
+
+ r->skip_reinit = true;
+
+ return 0;
+
+pm_put:
+ pm_runtime_put(dev);
+reset_assert:
+ reset_control_assert(r->rstc);
+ return ret;
+}
+
+static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
+};
+
+static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
+ { .compatible = "renesas,r9a09g047-usb3-phy" },
+ { /* Sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, rzg3e_phy_usb3_match_table);
+static struct platform_driver rzg3e_phy_usb3_driver = {
+ .driver = {
+ .name = "phy_rzg3e_usb3",
+ .of_match_table = rzg3e_phy_usb3_match_table,
+ .pm = pm_sleep_ptr(&rzg3e_phy_usb3_pm),
+ },
+ .probe = rzg3e_phy_usb3_probe,
+};
+module_platform_driver(rzg3e_phy_usb3_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Renesas RZ/G3E USB3.0 PHY Driver");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
2026-03-12 15:35 ` [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
@ 2026-03-18 10:02 ` Pavel Machek
2026-03-18 10:58 ` Biju Das
0 siblings, 1 reply; 16+ messages in thread
From: Pavel Machek @ 2026-03-18 10:02 UTC (permalink / raw)
To: Biju; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar
[-- Attachment #1: Type: text/plain, Size: 862 bytes --]
Hi!
> Add Renesas RZ/G3E USB3.0 PHY driver. This module is connected
> between USB3 Host and PHY module. The main functions of this
> module are:
> 1) Reset control
> 2) Control of PHY input pins
> 3) Monitoring of PHY output pins
> +++ b/drivers/phy/renesas/Kconfig
> @@ -40,3 +40,10 @@ config PHY_RCAR_GEN3_USB3
> select GENERIC_PHY
> help
> Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
> +
> +config PHY_RZ_G3E_USB3
> + tristate "Renesas RZ/G3E USB 3.0 PHY driver"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + select GENERIC_PHY
> + help
> + Support for USB 3.0 PHY found on Renesas RZ/G3E SoCs.
We usually have notice about module name here.
> +++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
> +MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
This should include real name and "<".
Thanks and best regards,
Pavel
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* RE: [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
2026-03-18 10:02 ` Pavel Machek
@ 2026-03-18 10:58 ` Biju Das
0 siblings, 0 replies; 16+ messages in thread
From: Biju Das @ 2026-03-18 10:58 UTC (permalink / raw)
To: Pavel Machek, biju.das.au
Cc: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu,
Prabhakar Mahadev Lad
Hi Pavel,
Thanks for the feedback
> -----Original Message-----
> From: Pavel Machek <pavel@nabladev.com>
> Sent: 18 March 2026 10:02
> To: biju.das.au <biju.das.au@gmail.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel
> Machek <pavel@nabladev.com>; Biju Das <biju.das.jz@bp.renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
>
> Hi!
>
> > Add Renesas RZ/G3E USB3.0 PHY driver. This module is connected between
> > USB3 Host and PHY module. The main functions of this module are:
> > 1) Reset control
> > 2) Control of PHY input pins
> > 3) Monitoring of PHY output pins
>
> > +++ b/drivers/phy/renesas/Kconfig
> > @@ -40,3 +40,10 @@ config PHY_RCAR_GEN3_USB3
> > select GENERIC_PHY
> > help
> > Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
> > +
> > +config PHY_RZ_G3E_USB3
> > + tristate "Renesas RZ/G3E USB 3.0 PHY driver"
> > + depends on ARCH_RENESAS || COMPILE_TEST
> > + select GENERIC_PHY
> > + help
> > + Support for USB 3.0 PHY found on Renesas RZ/G3E SoCs.
>
> We usually have notice about module name here.
Only few modules in PHY subsystem have this. Majority of the drivers won't use it.
$ fgrep -r "module will be" drivers/phy/
drivers/phy/allwinner/Kconfig: MIPI-DSI support. If M is selected, the module will be
drivers/phy/apple/Kconfig: If M is selected the module will be called 'phy-apple-atc'.
drivers/phy/starfive/Kconfig: system. If M is selected, the module will be called
drivers/phy/starfive/Kconfig: system. If M is selected, the module will be called
drivers/phy/starfive/Kconfig: If M is selected, the module will be called
drivers/phy/starfive/Kconfig: If M is selected, the module will be called
drivers/phy/mediatek/Kconfig: module will be called phy-mtk-mipi-csi-0-5.
drivers/phy/cadence/Kconfig: system. If M is selected, the module will be called
>
> > +++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
>
> > +MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
>
> This should include real name and "<".
OK will update as
MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
Cheers,
Biju
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6.12.y-cip 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (7 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 08/11] phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Biju
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 87c83a27b80062d0ca5dca408b7a7db42027a582 ]
Add USB3 PHY/Host nodes to RZ/G3E ("R9A09G047") SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250916150255.4231-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index addcc9ed8661..0a2fc3480a43 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1073,6 +1073,36 @@ gic: interrupt-controller@14900000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ xhci: usb@15850000 {
+ compatible = "renesas,r9a09g047-xhci";
+ reg = <0 0x15850000 0 0x10000>;
+ interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "all", "smi", "hse", "pme", "xhc";
+ clocks = <&cpg CPG_MOD 0xaf>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ phys = <&usb3_phy>, <&usb3_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3_phy: usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0 0x15870000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>,
+ <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sdhi0: mmc@15c00000 {
compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
reg = <0x0 0x15c00000 0 0x10000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (8 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Biju
@ 2026-03-12 15:35 ` Biju
2026-03-12 15:35 ` [PATCH 6.12.y-cip 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver Biju
2026-03-18 10:03 ` [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Pavel Machek
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 6ea91acf0f67a7e6dd1e899955346e00778d7b0f ]
Enable USB3.2 Gen2 Host controller(a.k.a USB3HOST) on the RZ/G3E SMARC EVK
platform.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250916150255.4231-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 10 ++++++++++
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 342b885006e9..696903dc7a63 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -196,6 +196,11 @@ sd1-data {
<RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
};
};
+
+ usb3_pins: usb3 {
+ pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
+ <RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
+ };
};
#if SW_SER0_PMOD && SW_SER2_EN
@@ -242,3 +247,8 @@ &sdhi1 {
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
+
+&xhci {
+ pinctrl-0 = <&usb3_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 69c0101ff7f5..b607b5d6c259 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -107,3 +107,11 @@ &sdhi1 {
status = "okay";
};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6.12.y-cip 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (9 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Biju
@ 2026-03-12 15:35 ` Biju
2026-03-18 10:03 ` [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Pavel Machek
11 siblings, 0 replies; 16+ messages in thread
From: Biju @ 2026-03-12 15:35 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 4e9153de25bf3c89b90f63cb4d155abc7f1a2117 ]
Enable the RZ/G3E USB3 PHY driver on the Renesas RZ/G3E SMARC EVK board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250916150255.4231-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 59b72226b5be..9ee6d08ba8cc 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1564,6 +1564,7 @@ CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_RZ_G3E_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support
2026-03-12 15:35 [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Biju
` (10 preceding siblings ...)
2026-03-12 15:35 ` [PATCH 6.12.y-cip 11/11] arm64: defconfig: Enable RZ/G3E USB3 PHY driver Biju
@ 2026-03-18 10:03 ` Pavel Machek
2026-03-18 21:59 ` [cip-dev] " Nobuhiro Iwamatsu (Toshiba)
11 siblings, 1 reply; 16+ messages in thread
From: Pavel Machek @ 2026-03-18 10:03 UTC (permalink / raw)
To: Biju; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar
[-- Attachment #1: Type: text/plain, Size: 479 bytes --]
Hi!
> Add RZ/G3E USB3.2 Gen1 Host Controller and PHY support. The USB3HOST
> is compliant with the Universal Serial Bus 3.2 Specification Revision 1.0.
I had some minor comments here, but those should be fixed in mainline,
first, so they should not block the merge.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
I can apply the series if it passes testing and there are no other
comments.
Best regards,
Pavel
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [cip-dev] [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support
2026-03-18 10:03 ` [PATCH 6.12.y-cip 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support Pavel Machek
@ 2026-03-18 21:59 ` Nobuhiro Iwamatsu (Toshiba)
0 siblings, 0 replies; 16+ messages in thread
From: Nobuhiro Iwamatsu (Toshiba) @ 2026-03-18 21:59 UTC (permalink / raw)
To: pavel; +Cc: Biju, cip-dev, Nobuhiro Iwamatsu, Biju Das, Lad Prabhakar
Hi all,
2026年3月18日(水) 19:03 Pavel Machek via lists.cip-project.org
<pavel=nabladev.com@lists.cip-project.org>:
>
> Hi!
>
> > Add RZ/G3E USB3.2 Gen1 Host Controller and PHY support. The USB3HOST
> > is compliant with the Universal Serial Bus 3.2 Specification Revision 1.0.
>
> I had some minor comments here, but those should be fixed in mainline,
> first, so they should not block the merge.
>
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
>
> I can apply the series if it passes testing and there are no other
> comments.
>
I reviewed this series, looks good to me too.
I applied with Pavel's reviewed-by tag, thanks.
> Best regards,
> Pavel
>
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 16+ messages in thread