[PATCH 6.1.y-cip 0/7] Add RZ/V2N TSU support

[PATCH 6.1.y-cip 0/7] Add RZ/V2N TSU support

[Ovidiu Panait]

Hi,

This series adds TSU support for the Renesas RZ/V2N SoC.

All patches, except for patches 4/7 and 6/7, were cherry-picked
from mainline kernel.

The RZ/V2H binding patch (1/7) was missed during RZ/V2H TSU backporting,
so it was added in this series.

Patch 4/7 is needed to fix asynchronous aborts during unbind. See the MSTOP
series for more details:
https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.beznea.uj@bp.renesas.com/

Patch 6/7 is a backport specific change that is needed to allow the
thermal driver to read calibration data from the system controller.

Best regards,
Ovidiu

Kuninori Morimoto (1):
  arm64: dts: renesas: r9a09g056: Move interrupt-parent to root node

Ovidiu Panait (6):
  dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2H TSU
  dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2N TSU
  clk: renesas: r9a09g056: Add clock and reset entries for TSU
  PM: domains: Add RZ/V2N compatible to PM domain detach list
  arm64: dts: renesas: r9a09g056: Use syscon compatible for the system
    controller
  arm64: dts: renesas: r9a09g056: Add TSU nodes

 .../thermal/renesas,r9a09g047-tsu.yaml        |  8 +-
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 89 +++++++++++++++++--
 drivers/base/power/common.c                   |  1 +
 drivers/clk/renesas/r9a09g056-cpg.c           |  6 ++
 4 files changed, 96 insertions(+), 8 deletions(-)

-- 
2.51.0

[PATCH 6.1.y-cip 1/7] dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2H TSU

[Ovidiu Panait]

commit 30183a67a8a0e74adf92e2dc66b5674465d42025 upstream.

The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing.

The Renesas RZ/V2H SoC is using the same TSU IP found on the RZ/G3E SoC,
the only difference being that it has two channels instead of one.

Add new compatible string "renesas,r9a09g057-tsu" for RZ/V2H and use
"renesas,r9a09g047-tsu" as a fallback compatible to indicate hardware
compatibility with the RZ/G3E implementation.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251020143107.13974-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 .../devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml  | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
index 8d3f3c24f0f2..befdc8b7a082 100644
--- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
@@ -16,7 +16,11 @@ description:
 
 properties:
   compatible:
-    const: renesas,r9a09g047-tsu
+    oneOf:
+      - const: renesas,r9a09g047-tsu # RZ/G3E
+      - items:
+          - const: renesas,r9a09g057-tsu # RZ/V2H
+          - const: renesas,r9a09g047-tsu # RZ/G3E
 
   reg:
     maxItems: 1
-- 
2.51.0

[PATCH 6.1.y-cip 2/7] dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2N TSU

[Ovidiu Panait]

commit 96b0bb4a2310302307bafe62edbc3455fae8b723 upstream.

The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing.

The Renesas RZ/V2N SoC is using the same TSU IP found on the RZ/G3E SoC,
the only difference being that it has two channels instead of one.

Add new compatible string "renesas,r9a09g056-tsu" for RZ/V2N and use
"renesas,r9a09g047-tsu" as a fallback compatible to indicate hardware
compatibility with the RZ/G3E implementation.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 .../devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml    | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
index befdc8b7a082..c959b9834620 100644
--- a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
+++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml
@@ -19,7 +19,9 @@ properties:
     oneOf:
       - const: renesas,r9a09g047-tsu # RZ/G3E
       - items:
-          - const: renesas,r9a09g057-tsu # RZ/V2H
+          - enum:
+              - renesas,r9a09g056-tsu # RZ/V2N
+              - renesas,r9a09g057-tsu # RZ/V2H
           - const: renesas,r9a09g047-tsu # RZ/G3E
 
   reg:
-- 
2.51.0

[PATCH 6.1.y-cip 3/7] clk: renesas: r9a09g056: Add clock and reset entries for TSU

[Ovidiu Panait]

commit ebb3acf4d7c95b52265084168b59a565bf972883 upstream.

Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/clk/renesas/r9a09g056-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 651f5efc34bc..1c2b7c3a3821 100644
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -374,6 +374,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
 						BUS_MSTOP(3, BIT(4))),
 	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
 						BUS_MSTOP(3, BIT(4))),
+	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,
+						BUS_MSTOP(5, BIT(2))),
+	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
+						BUS_MSTOP(2, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
@@ -426,6 +430,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
 	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */
 	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */
 	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */
+	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */
+	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
-- 
2.51.0

[PATCH 6.1.y-cip 4/7] PM: domains: Add RZ/V2N compatible to PM domain detach list

[Ovidiu Panait]

Add Renesas RZ/V2N compatible to the PM domain detach list in
dev_pm_domain_allow_detach_on_unbind_cleanup(). This fixes asynchronous
aborts when unbinding the TSU devices.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/base/power/common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
index 44c485f0c96b..e83ba3a5611f 100644
--- a/drivers/base/power/common.c
+++ b/drivers/base/power/common.c
@@ -246,6 +246,7 @@ bool dev_pm_domain_allow_detach_on_unbind_cleanup(void)
 		"renesas,r9a07g054", /* Renesas RZ/V2L */
 		"renesas,r9a08g045", /* Renesas RZ/G3S */
 		"renesas,r9a09g047", /* Renesas RZ/G3E */
+		"renesas,r9a09g056", /* Renesas RZ/V2N */
 		"renesas,r9a09g057", /* Renesas RZ/V2H */
 		NULL
 	};
-- 
2.51.0

Re: [PATCH 6.1.y-cip 4/7] PM: domains: Add RZ/V2N compatible to PM domain detach list

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 1108 bytes --]

On Wed 2026-04-08 09:39:47, Ovidiu Panait wrote:
> Add Renesas RZ/V2N compatible to the PM domain detach list in
> dev_pm_domain_allow_detach_on_unbind_cleanup(). This fixes asynchronous
> aborts when unbinding the TSU devices.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>

Aha, so this one is not upstream because these power management
changes are -cip, only. This confused me for a while, would be worth
noting here.

Thanks and best regards,
								Pavel

> ---
>  drivers/base/power/common.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/base/power/common.c b/drivers/base/power/common.c
> index 44c485f0c96b..e83ba3a5611f 100644
> --- a/drivers/base/power/common.c
> +++ b/drivers/base/power/common.c
> @@ -246,6 +246,7 @@ bool dev_pm_domain_allow_detach_on_unbind_cleanup(void)
>  		"renesas,r9a07g054", /* Renesas RZ/V2L */
>  		"renesas,r9a08g045", /* Renesas RZ/G3S */
>  		"renesas,r9a09g047", /* Renesas RZ/G3E */
> +		"renesas,r9a09g056", /* Renesas RZ/V2N */
>  		"renesas,r9a09g057", /* Renesas RZ/V2H */
>  		NULL
>  	};

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[PATCH 6.1.y-cip 5/7] arm64: dts: renesas: r9a09g056: Move interrupt-parent to root node

[Ovidiu Panait]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

commit e45e76a02b28b76a48b23b03e5cea8df84a5ba04 upstream.

Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/87frcc8o8b.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index bb1a0cac3076..a08d10950651 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -30,6 +30,7 @@ / {
 	compatible = "renesas,r9a09g056";
 	#address-cells = <2>;
 	#size-cells = <2>;
+	interrupt-parent = <&gic>;
 
 	audio_extal_clk: audio-clk {
 		compatible = "fixed-clock";
@@ -173,7 +174,6 @@ rtxin_clk: rtxin-clk {
 
 	soc: soc {
 		compatible = "simple-bus";
-		interrupt-parent = <&gic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
@@ -1334,11 +1334,11 @@ stmmac_axi_setup: stmmac-axi-config {
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
-				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
 	};
 };
-- 
2.51.0

[PATCH 6.1.y-cip 6/7] arm64: dts: renesas: r9a09g056: Use syscon compatible for the system controller

[Ovidiu Panait]

The Renesas RZ/V2N TSU driver needs the system controller syscon
to be able to retrieve calibration data. For this, it uses
syscon_regmap_lookup_by_phandle_args(). But, in v6.1 CIP,
syscon_regmap_lookup_by_phandle_args() returns ERR_PTR(-EINVAL) if
the node for which it is called doesn't have the syscon compatible.

Therefore, add syscon compatible for the system controller.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index a08d10950651..0d60d4cdb257 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -292,7 +292,7 @@ cpg: clock-controller@10420000 {
 		};
 
 		sys: system-controller@10430000 {
-			compatible = "renesas,r9a09g056-sys";
+			compatible = "renesas,r9a09g056-sys", "syscon";
 			reg = <0 0x10430000 0 0x10000>;
 			clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>;
 			resets = <&cpg 0x30>;
-- 
2.51.0

[PATCH 6.1.y-cip 7/7] arm64: dts: renesas: r9a09g056: Add TSU nodes

[Ovidiu Panait]

commit f3d22e5f6392d05d61438455bce40bfb766bf2b4 upstream.

The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing:
- TSU0, which is located near the DRP-AI block
- TSU1, which is located near the CPU and DRP-AI block

Since TSU1 is physically closer the CPU and the highest temperature
spot, it is used for CPU throttling through a passive trip and cooling
map. TSU0 is configured only with a critical trip.

Add TSU nodes along with thermal zones and keep them enabled in the SoC
DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-4-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 75 ++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 0d60d4cdb257..d69b3d3d1835 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -83,6 +83,7 @@ cpu0: cpu@0 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -93,6 +94,7 @@ cpu1: cpu@100 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -103,6 +105,7 @@ cpu2: cpu@200 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -113,6 +116,7 @@ cpu3: cpu@300 {
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
+			#cooling-cells = <2>;
 			operating-points-v2 = <&cluster0_opp>;
 		};
 
@@ -298,6 +302,32 @@ sys: system-controller@10430000 {
 			resets = <&cpg 0x30>;
 		};
 
+		tsu0: thermal@11000000 {
+			compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu";
+			reg = <0 0x11000000 0 0x1000>;
+			interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x109>;
+			resets = <&cpg 0xf7>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x320>;
+		};
+
+		tsu1: thermal@14002000 {
+			compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu";
+			reg = <0 0x14002000 0 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "adi", "adcmpi";
+			clocks = <&cpg CPG_MOD 0x10a>;
+			resets = <&cpg 0xf8>;
+			power-domains = <&cpg>;
+			#thermal-sensor-cells = <0>;
+			renesas,tsu-trim = <&sys 0x330>;
+		};
+
 		xspi: spi@11030000 {
 			compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
 			reg = <0 0x11030000 0 0x10000>,
@@ -1332,6 +1362,51 @@ stmmac_axi_setup: stmmac-axi-config {
 		snps,blen = <16 8 4 0 0 0 0>;
 	};
 
+	thermal-zones {
+		sensor1_thermal: sensor1-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu0>;
+
+			trips {
+				sensor1_crit: sensor1-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		sensor2_thermal: sensor2-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <250>;
+			thermal-sensors = <&tsu1>;
+
+			cooling-maps {
+				map0 {
+					trip = <&sensor2_target>;
+					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+							 <&cpu2 0 3>, <&cpu3 0 3>;
+					contribution = <1024>;
+				};
+			};
+
+			trips {
+				sensor2_target: trip-point {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				sensor2_crit: sensor2-crit {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-- 
2.51.0

Re: [PATCH 6.1.y-cip 0/7] Add RZ/V2N TSU support

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 942 bytes --]

Hi!

> This series adds TSU support for the Renesas RZ/V2N SoC.
> 
> All patches, except for patches 4/7 and 6/7, were cherry-picked
> from mainline kernel.
> 
> The RZ/V2H binding patch (1/7) was missed during RZ/V2H TSU backporting,
> so it was added in this series.
> 
> Patch 4/7 is needed to fix asynchronous aborts during unbind. See the MSTOP
> series for more details:
> https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.beznea.uj@bp.renesas.com/
> 
> Patch 6/7 is a backport specific change that is needed to allow the
> thermal driver to read calibration data from the system controller.

Aha, explanation is here, I just missed it. Sorry for noise.

Series looks okay to me.

Reviewed-by: Pavel Machek <pavel@nabladev.com>

I can apply the series if it passes testing and there are no other
comments.

Best regards,
                                                                Pavel


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RE: [cip-dev] [PATCH 6.1.y-cip 0/7] Add RZ/V2N TSU support

[nobuhiro.iwamatsu.x90]

Hi all,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Wednesday, April 8, 2026 7:48 PM
> To: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Cc: cip-dev@lists.cip-project.org; pavel@nabladev.com; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro.iwamatsu.x90@mail.toshiba>
> Subject: Re: [cip-dev] [PATCH 6.1.y-cip 0/7] Add RZ/V2N TSU support
> 
> Hi!
> 
> > This series adds TSU support for the Renesas RZ/V2N SoC.
> >
> > All patches, except for patches 4/7 and 6/7, were cherry-picked from
> > mainline kernel.
> >
> > The RZ/V2H binding patch (1/7) was missed during RZ/V2H TSU
> > backporting, so it was added in this series.
> >
> > Patch 4/7 is needed to fix asynchronous aborts during unbind. See the
> > MSTOP series for more details:
> > https://lore.kernel.org/cip-dev/20260115083451.1064048-1-claudiu.bezne
> > a.uj@bp.renesas.com/
> >
> > Patch 6/7 is a backport specific change that is needed to allow the
> > thermal driver to read calibration data from the system controller.
> 
> Aha, explanation is here, I just missed it. Sorry for noise.
> 
> Series looks okay to me.
> 
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
> 
> I can apply the series if it passes testing and there are no other comments.

I reviewed this series, looks good to me too.
I applied with Pavel's reviewed-by tag.

> 
> Best regards,
>                                                                 Pavel

Best regards,
  Nobuhiro