Re: [PATCH 6.12.y-cip 15/23] pinctrl: renesas: rzg2l: Add support for clone channel control

[Pavel Machek <pavel@nabladev.com>]

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Hi!
> The RZ/G3L SoC has some IP such as I2C ch{2,3},SCIF ch{3,4,5},
> RSPI ch{1,2} and RSCI ch{1,2,3} need to control the clone channel for
> proper operation. As per the RZ/G3L hardware manual, the clone channel
> setting is to be done before the mux setting.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Link: https://patch.msgid.link/20260430093422.74812-8-biju.das.jz@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

...

> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -352,6 +368,7 @@ struct rzg2l_pinctrl_pin_settings {
>   * @smt: SMT registers cache
>   * @sr: SR registers cache
>   * @nod: NOD registers cache
> + * @clone: Clone register cache
>   * @sd_ch: SD_CH registers cache

I notice clone is very different from the other fields (being value,
not pointer), yet is documented in exactly the same way as other
field. That should probably be improved.

>   * @eth_poc: ET_POC registers cache
>   * @other_poc: OTHER_POC register cache
> @@ -369,6 +386,7 @@ struct rzg2l_pinctrl_reg_cache {
>  	u32	*smt[2];
>  	u32	*sr[2];
>  	u32	*nod[2];
> +	u32	clone;
>  	u8	sd_ch[2];
>  	u8	eth_poc[2];
>  	u8	oen;
> @@ -387,6 +405,8 @@ struct rzg2l_pinctrl {
>  
>  	struct clk			*clk;
>  
> +	struct regmap			*syscon;
> +
>  	struct gpio_chip		gpio_chip;
>  	struct pinctrl_gpio_range	gpio_range;
>  	DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);

Best regards,
								Pavel

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