From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Pavel Machek <pavel@nabladev.com>
Cc: nobuhiro.iwamatsu.x90@mail.toshiba, cip-dev@lists.cip-project.org
Subject: Re: [PATCH 5.10.y-cip 05/28] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config
Date: Wed, 25 Mar 2026 10:35:47 +0200 [thread overview]
Message-ID: <c78b03d4-045d-423e-9265-156641ae8dae@tuxon.dev> (raw)
In-Reply-To: <acJYvRx1EYafqZD_@duo.ucw.cz>
Hi, Pavel,
On 3/24/26 11:26, Pavel Machek wrote:
> Hi1
>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> commit c432180a7d95081353a96fd6d5bd75b0fc8a27c3 upstream.
>>
>> Not all system controller registers are accessible from Linux. Accessing
>> such registers generates synchronous external abort. Populate the
>> readable_reg and writeable_reg members of the regmap config to inform the
>> regmap core which registers can be accessed. The list will need to be
>> updated whenever new system controller functionality is exported through
>> regmap.
>>
>
>> +++ b/drivers/soc/renesas/r9a08g045-sysc.c
>> @@ -18,7 +37,57 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
>> .specific_id_mask = GENMASK(27, 0),
>> };
>>
>> +static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case SYS_XSPI_MAP_STAADD_CS0:
>> + case SYS_XSPI_MAP_ENDADD_CS0:
>> + case SYS_XSPI_MAP_STAADD_CS1:
>> + case SYS_XSPI_MAP_ENDADD_CS1:
>> + case SYS_GETH0_CFG:
>> + case SYS_GETH1_CFG:
>> + case SYS_PCIE_CFG:
>> + case SYS_PCIE_MON:
>> + case SYS_PCIE_ERR_MON:
>> + case SYS_PCIE_PHY:
>> + case SYS_I2C0_CFG:
>> + case SYS_I2C1_CFG:
>> + case SYS_I2C2_CFG:
>> + case SYS_I2C3_CFG:
>> + case SYS_I3C_CFG:
>> + case SYS_USB_PWRRDY:
>> + case SYS_PCIE_RST_RSM_B:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool rzg3s_regmap_writeable_reg(struct device *dev, unsigned int reg)
>> +{
>> + switch (reg) {
>> + case SYS_XSPI_MAP_STAADD_CS0:
>> + case SYS_XSPI_MAP_ENDADD_CS0:
>> + case SYS_XSPI_MAP_STAADD_CS1:
>> + case SYS_XSPI_MAP_ENDADD_CS1:
>> + case SYS_PCIE_CFG:
>> + case SYS_PCIE_PHY:
>> + case SYS_I2C0_CFG:
>> + case SYS_I2C1_CFG:
>> + case SYS_I2C2_CFG:
>> + case SYS_I2C3_CFG:
>> + case SYS_I3C_CFG:
>> + case SYS_USB_PWRRDY:
>> + case SYS_PCIE_RST_RSM_B:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>
> I'd not mind refactoring these two so that code could be shared.
OK, I'm going to prepare something for upstream.
Thank you for your review,
Claudiu
next prev parent reply other threads:[~2026-03-25 8:35 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 11:03 [PATCH 5.10.y-cip 00/28] Add RZ/G3S PCIe support Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 01/28] soc: renesas: Add SYSC driver for Renesas RZ family Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 02/28] soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 03/28] mfd: syscon: Add of_syscon_register_regmap() API Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 04/28] soc: renesas: rz-sysc: Add syscon/regmap support Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 05/28] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config Claudiu
2026-03-24 9:26 ` Pavel Machek
2026-03-25 8:35 ` Claudiu Beznea [this message]
2026-03-11 11:03 ` [PATCH 5.10.y-cip 06/28] clk: renesas: r9a08g045: Add PCIe clocks and resets Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 07/28] lib/bitmap: add bitmap_{read,write}() Claudiu
2026-03-24 9:29 ` Pavel Machek
2026-03-25 8:37 ` Claudiu Beznea
2026-03-11 11:03 ` [PATCH 5.10.y-cip 08/28] genirq/msi: Silence 'set affinity failed' warning Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 09/28] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Claudiu
2026-03-24 9:33 ` Pavel Machek
2026-03-25 8:36 ` Claudiu Beznea
2026-03-11 11:03 ` [PATCH 5.10.y-cip 10/28] PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 11/28] PCI: Move link up wait time and max retries macros to pci.h Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 12/28] reset: make shared pulsed reset controls re-triggerable Claudiu
2026-03-24 9:37 ` Pavel Machek
2026-03-25 8:35 ` Claudiu Beznea
2026-03-11 11:03 ` [PATCH 5.10.y-cip 13/28] reset: Add reset_control_bulk API Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 14/28] of: Add cleanup.h based auto release via __free(device_node) markings Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 15/28] of/irq: Allow matching of an interrupt-map local to an interrupt controller Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 16/28] of/irq: Update the out_irq->np before returning success Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 17/28] dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 18/28] PCI: Add Renesas RZ/G3S host controller driver Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 19/28] PCI: rzg3s-host: Initialize MSI status bitmap before use Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 20/28] PCI: rzg3s-host: Use pci_generic_config_write() for the root bus Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 21/28] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 22/28] PCI: rzg3s-host: Fix device node reference leak in rzg3s_pcie_host_parse_port() Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 23/28] arm64: dts: renesas: r9a08g045: Enable SYS node Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 24/28] arm64: dts: renesas: r9a08g045: Use syscon compatible for the system controller Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 25/28] arm64: dts: renesas: r9a08g045: Add PCIe node Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 26/28] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 27/28] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2026-03-11 11:03 ` [PATCH 5.10.y-cip 28/28] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
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