From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dirk Brandewie Subject: Re: Clarification on the DVFS capabilities Date: Tue, 28 May 2013 08:09:15 -0700 Message-ID: <51A4C89B.8090502@intel.com> References: Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=TSlL1T+UAxmGec+Z3hwDEgqBP0LgLMms98mSnb1FkIo=; b=f5rmHUgpbdee4w/yuBvQ2t3S5IdLJJnQuKTO4Dj+O7UoB1GFhQR8faQx3kvO0BzhQF mFRHX8Ciki4qg30GvnUPaD9Y/4UHZhuL4m1+5gOFr9saPq9/MwqKzIpRayRr9FXddF9O MPhleypfG6BYiRVPjxYc4jEdBEUnNmSYDQP3UCf+TZ8hxKEbJU0c224ZQjqaCeaBEHwy QrUfn0NNiuF/PmFX2Z2fn1anHTH8Qit12d4sv0J5wyu3daTd/sWLsfO/AVHhsVWoL7Ss tjnK1PQiWdj2T9yh+wiPMwy+907VisgtZtbaYrgH5nK+pTs+oB8ooHoDR2bb1hS8ijI/ JeUQ== In-Reply-To: Sender: cpufreq-owner@vger.kernel.org List-ID: Content-Type: text/plain; charset="us-ascii"; format="flowed" To: karthik vm Cc: Viresh Kumar , cpufreq On 05/26/2013 05:20 PM, karthik vm wrote: > Thanks for your insights Viresh & Dirk. I really appreciate it. > > I read from the net that the p-state (Voltage/Frequency) pairs in > Intel processors(e.g Nehalem) cannot be set for individual cores > (http://web.archive.org/web/20130527001342/http://people.cs.pitt.edu/~kirk/cs3150spring2010/ShiminChen.pptx). > > As Dirk pointed out, each core may request a p-state but ultimately > all the whole processor's p-state is set to the minimum of the > requested p-states. But in my Core2Duo processor, I see that two cores > are in different frequencies(p-state) and it did not fit into the > explanation above :-(. I think I am missing something. The requested p-state is being reported which is individually controllable AFAIK there is no way to get the instantaneous operation frequncy of the package. You can look at the APERF/MPERF to tell what effective frequency the core ran at over a sample time but that is the closet you can get to the actual frequency the core "is" runing at. > > Regards, > karthik > > On Sun, May 26, 2013 at 3:01 AM, Viresh Kumar wrote: >> On 26 May 2013 05:30, karthik vm wrote: >>> Thanks for your insights Viresh. I really appreciate it!! >>> >>> Basically I wanted to know the DVFS granularity of a multi-core chip. >>> i.e I want to know whether every core can separately increase or >>> decrease its frequency or all the cores increase or decrease >>> simultaneously. I think cpufreq-info command's output "CPUs which need >>> to have their frequency coordinated by software" gives the answer. For >>> my core2duo processor it says either core 0 or core 1. Hence frequency >>> of each of my cores can be changed individually. Experimental results >>> also supports it. Please correct me if there is any fallacy in my >>> inference. >> >> Whether cores can have separate control of clks or not is decided by >> hardware implementation. On ARM normally all cores within a cluster >> have common control of clk lines.. On Intel, I am not sure. >> >> Now, the hardware can have interesting capabilities where they can >> manage separate clk lines themselves and software doesn't need to >> do anything special for them. And so that's what Dirk pointed out >> earlier. >> >> Your observation looks correct though.