From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kukjin Kim Subject: Re: [PATCH 1/3] ARM: EXYNOS: Add exynos5 CPU clock divider offsets Date: Sat, 21 Dec 2013 06:23:44 +0900 Message-ID: <52B4B560.6030001@samsung.com> References: <1386323284-15646-1-git-send-email-arun.kk@samsung.com> <1386323284-15646-2-git-send-email-arun.kk@samsung.com> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=mXcUzsoy45g8RnrnYScOahWgoPp3zjc2diWCHkz1Afo=; b=B+kl1OKtqoqF73CxLnWh1m8CHNA3OowG982xf/MbPVSQp+AeVasF9+3h+TJQZxAEvB SrVsfCu/ZMVWOQNpfBQClq9AeqN0GDI1VyGyQjD8FTw0UIAjiDOXtyX/E8HeiyFx4EeL FhcCbvWvqk+oGeCP7kkTEWdWYknf8NjT7X5IVbzRYze93wCLF9RH0vjN3659R7MUXRuE 0wwMVACgaAR++JiIzPiZJkahZ93Mw6nMQusECm1vsTnx5ry/b3peq+WpYcYyKo1Nz35v exeYShLQJVeOVwMvXpv5kBjkS9vdDOi7zDRWebcRwC5zE2/+bhRoJ3737fa56vXundLV HghA== In-Reply-To: <1386323284-15646-2-git-send-email-arun.kk@samsung.com> Sender: cpufreq-owner@vger.kernel.org List-ID: Content-Type: text/plain; charset="us-ascii"; format="flowed" To: Arun Kumar K Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cpufreq@vger.kernel.org, kgene.kim@samsung.com, mturquette@linaro.org, abrestic@chromium.org, viresh.kumar@linaro.org, arunkk.samsung@gmail.com, rjw@rjwysocki.net, tomasz.figa@gmail.com, arjun.kv@samsung.com On 12/06/13 18:48, Arun Kumar K wrote: > Adds the CPU clock divider shifts and masks for Exynos5 SoC. > These defines will be used in cpufreq driver. > > Signed-off-by: Arjun.K.V > Signed-off-by: Arun Kumar K > --- > arch/arm/mach-exynos/include/mach/regs-clock.h | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h > index d36ad76..d0186d3 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-clock.h > +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h > @@ -347,6 +347,30 @@ > > #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) > > +/* CLK_DIV_CPU0 */ > +#define EXYNOS5_CLKDIV_CPU0_CORE_SHIFT 0 > +#define EXYNOS5_CLKDIV_CPU0_CORE_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_CORE_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT 4 > +#define EXYNOS5_CLKDIV_CPU0_CPUD_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_ACP_SHIFT 8 > +#define EXYNOS5_CLKDIV_CPU0_ACP_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_ACP_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_ATB_SHIFT 16 > +#define EXYNOS5_CLKDIV_CPU0_ATB_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_ATB_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT 20 > +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_APLL_SHIFT 24 > +#define EXYNOS5_CLKDIV_CPU0_APLL_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_APLL_SHIFT) > +#define EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT 28 > +#define EXYNOS5_CLKDIV_CPU0_CORE2_MASK (0x7<< EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT) > + > +/* CLK_DIV_CPU1 */ > +#define EXYNOS5_CLKDIV_CPU1_COPY_SHIFT 0 > +#define EXYNOS5_CLKDIV_CPU1_COPY_MASK (0x7<< EXYNOS5_CLKDIV_CPU1_COPY_SHIFT) > +#define EXYNOS5_CLKDIV_CPU1_HPM_SHIFT 4 > +#define EXYNOS5_CLKDIV_CPU1_HPM_MASK (0x7<< EXYNOS5_CLKDIV_CPU1_HPM_SHIFT) > +#define EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT 16 > +#define EXYNOS5_CLKMUX_STATCPU_MUXCORE_MASK (0x7<< EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT) > + > #define PWR_CTRL1_CORE2_DOWN_RATIO (7<< 28) > #define PWR_CTRL1_CORE1_DOWN_RATIO (7<< 16) > #define PWR_CTRL1_DIV2_DOWN_EN (1<< 9) Hi Arun, Above definitions should be moved into regarding driver not into arch. Please see my current for-next, there is no . Thanks, Kukjin