* Re: [PATCH] schemas: PCI: Add standard PCIe WAKE# signal
2025-05-15 9:05 [PATCH] schemas: PCI: Add standard PCIe WAKE# signal Krishna Chaitanya Chundru
@ 2025-05-28 4:50 ` Krishna Chaitanya Chundru
2025-06-09 13:16 ` Rob Herring
2025-06-09 14:37 ` Bjorn Helgaas
2 siblings, 0 replies; 4+ messages in thread
From: Krishna Chaitanya Chundru @ 2025-05-28 4:50 UTC (permalink / raw)
To: robh
Cc: linux-arm-msm, helgaas, krzk, manivannan.sadhasivam, devicetree,
dmitry.baryshkov, lpieralisi, kw, conor+dt, linux-pci,
linux-kernel, devicetree-spec, quic_vbadigan, andersson,
sherry.sun
On 5/15/2025 2:35 PM, Krishna Chaitanya Chundru wrote:
> As per PCIe spec 6, sec 5.3.3.2 document PCI standard WAKE# signal,
> which is used to re-establish power and reference clocks to the
> components within its domain.
>
Hi Rob,
can you check this patch once.
- Krishna Chaitanya.
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> dtschema/schemas/pci/pci-bus-common.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..a39fafc 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -142,6 +142,10 @@ properties:
> description: GPIO controlled connection to PERST# signal
> maxItems: 1
>
> + wake-gpios:
> + description: GPIO controlled connection to WAKE# signal
> + maxItems: 1
> +
> slot-power-limit-milliwatt:
> description:
> If present, specifies slot power limit in milliwatts.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] schemas: PCI: Add standard PCIe WAKE# signal
2025-05-15 9:05 [PATCH] schemas: PCI: Add standard PCIe WAKE# signal Krishna Chaitanya Chundru
2025-05-28 4:50 ` Krishna Chaitanya Chundru
@ 2025-06-09 13:16 ` Rob Herring
2025-06-09 14:37 ` Bjorn Helgaas
2 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2025-06-09 13:16 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: andersson, dmitry.baryshkov, manivannan.sadhasivam, krzk, helgaas,
linux-arm-msm, devicetree, lpieralisi, kw, conor+dt, linux-pci,
linux-kernel, devicetree-spec, quic_vbadigan, sherry.sun
On Thu, May 15, 2025 at 02:35:17PM +0530, Krishna Chaitanya Chundru wrote:
> As per PCIe spec 6, sec 5.3.3.2 document PCI standard WAKE# signal,
> which is used to re-establish power and reference clocks to the
> components within its domain.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> dtschema/schemas/pci/pci-bus-common.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
Applied, thanks.
Rob
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] schemas: PCI: Add standard PCIe WAKE# signal
2025-05-15 9:05 [PATCH] schemas: PCI: Add standard PCIe WAKE# signal Krishna Chaitanya Chundru
2025-05-28 4:50 ` Krishna Chaitanya Chundru
2025-06-09 13:16 ` Rob Herring
@ 2025-06-09 14:37 ` Bjorn Helgaas
2 siblings, 0 replies; 4+ messages in thread
From: Bjorn Helgaas @ 2025-06-09 14:37 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: andersson, robh, dmitry.baryshkov, manivannan.sadhasivam, krzk,
linux-arm-msm, devicetree, lpieralisi, kw, conor+dt, linux-pci,
linux-kernel, devicetree-spec, quic_vbadigan, sherry.sun
On Thu, May 15, 2025 at 02:35:17PM +0530, Krishna Chaitanya Chundru wrote:
> As per PCIe spec 6, sec 5.3.3.2 document PCI standard WAKE# signal,
> which is used to re-establish power and reference clocks to the
> components within its domain.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> dtschema/schemas/pci/pci-bus-common.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..a39fafc 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -142,6 +142,10 @@ properties:
> description: GPIO controlled connection to PERST# signal
> maxItems: 1
>
> + wake-gpios:
> + description: GPIO controlled connection to WAKE# signal
"GPIO controlled" makes it sound like the GPIO can assert or deassert
the WAKE# signal. But isn't WAKE# driven ("controlled") by a PCIe
endpoint, and this GPIO would be input-only at the other end to sense
the state of WAKE#?
^ permalink raw reply [flat|nested] 4+ messages in thread