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Fri, 27 Feb 2026 04:41:01 -0800 (PST) Received: from [192.168.1.187] ([148.63.225.166]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4399c75b327sm7164780f8f.20.2026.02.27.04.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 04:41:00 -0800 (PST) Message-ID: <00863862d66cbb3393576d5dfbede9200f323b9d.camel@gmail.com> Subject: Re: [PATCH 0/5] dma: dma-axi-dmac: Add cyclic transfer support and graceful termination From: Nuno =?ISO-8859-1?Q?S=E1?= To: Vinod Koul , Nuno =?ISO-8859-1?Q?S=E1?= via B4 Relay Cc: dmaengine@vger.kernel.org, Lars-Peter Clausen Date: Fri, 27 Feb 2026 12:41:45 +0000 In-Reply-To: References: <20260127-axi-dac-cyclic-support-v1-0-b32daca4b3c7@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2026-02-27 at 07:47 +0530, Vinod Koul wrote: > On 27-01-26, 14:28, Nuno S=C3=A1 via B4 Relay wrote: > > This series adds support for cyclic transfers in the .device_prep_perip= heral_dma_vec() > > callback and implements graceful termination of cyclic transfers using = the > > DMA_PREP_LOAD_EOT flag. Using DMA_PREP_REPEAT and DMA_PREP_LOAD_EOT is > > based on the discussion in [1]. > >=20 > > Currently, the only way to stop a cyclic transfer is through brute forc= e using > > .device_terminate_all(), which terminates all pending transfers. This s= eries > > introduces a mechanism to gracefully terminate individual cyclic transf= ers when > > a new transfer flagged with DMA_PREP_LOAD_EOT is queued. > >=20 > > We need two different approaches: > >=20 > > 1. Software-managed cyclic transfers: These generate EOT (End-Of-Transf= er) > > =C2=A0=C2=A0 interrupts for each cycle. Hence, termination can be handl= ed directly > > =C2=A0=C2=A0 in the interrupt handler when the EOT interrupt fires, mak= ing the > > =C2=A0=C2=A0 transition to the next transfer straightforward. > >=20 > > 2. Hardware-managed cyclic transfers: These are optimized to avoid inte= rrupt > > =C2=A0=C2=A0 overhead by suppressing EOT interrupts. Since there are no= EOT interrupts, > > =C2=A0=C2=A0 termination must be detected at SOF (Start-Of-Frame) when = new transfers > > =C2=A0=C2=A0 are being considered. The transfer is marked for terminati= on and the > > =C2=A0=C2=A0 hardware is configured to end the current cycle gracefully= . > >=20 > > For HW-managed cyclic mode, the series handles both scatter-gather and = non-SG > > variants. With SG support, the last segment flags are modified to trigg= er EOT. > > Without SG, the CYCLIC flag is cleared to allow natural completion. A w= orkaround > > is included for older IP cores (pre-4.6.a) that can prefetch data incor= rectly > > when clearing the CYCLIC flag, requiring a core disable/enable cycle. > >=20 > > [1]: https://lore.kernel.org/dmaengine/ZhJW9JEqN2wrejvC@matsya/ > >=20 > > --- > > Nuno S=C3=A1 (5): > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dmaengine: Document cyclic transfer for = dmaengine_prep_peripheral_dma_vec() > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dma: dma-axi-dmac: add cyclic transfers = in .device_prep_peripheral_dma_vec() > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dma: dma-axi-dmac: add helper for gettin= g next desc > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dma: dma-axi-dmac: Gracefully terminate = SW cyclic transfers > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 dma: dma-axi-dmac: gracefully terminate = HW cyclic transfers >=20 > Please be consistent in naming, it should dmaengine: dma-axi-dmac: xxx > everywhere! Ahh sure! Sorry, not sure how I did not noticed such an obvious thing! - Nuno S=C3=A1