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([2a01:e0a:982:cbb0:fea4:bc29:4ea9:97a]) by smtp.gmail.com with ESMTPSA id j14-20020a05600c190e00b003dcc82ce53fsm1317774wmq.38.2023.02.08.01.08.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Feb 2023 01:08:21 -0800 (PST) Message-ID: <0f16d63f-3bb0-54aa-bcb4-4c666d4b2846@linaro.org> Date: Wed, 8 Feb 2023 10:08:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH] dt-bindings: dma: qcom,bam-dma: add optional memory interconnect properties Content-Language: en-US To: Krzysztof Kozlowski , Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230207-topic-sm8550-upstream-bam-dma-bindings-fix-v1-1-57dba71e8727@linaro.org> <88c31e71-55b6-a20d-1fcf-07804eace54b@linaro.org> Organization: Linaro Developer Services In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On 08/02/2023 10:03, Krzysztof Kozlowski wrote: > On 07/02/2023 16:27, Dmitry Baryshkov wrote: >> On 07/02/2023 15:35, Neil Armstrong wrote: >>> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>>> in order to have functional DMA. >>>>> >>>>> Signed-off-by: Neil Armstrong >>>>> --- >>>>>   Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>>>   1 file changed, 6 insertions(+) >>>> >>>> I suspect this will not work without a change for a driver. >>>> >>> >>> I had the impression single interconnect entries would be taken in account >>> by the platform core, but it doesn't seem to be the case, anyway I can;t >>> find >>> any code doing that. >> >> Probably you mixed interconnects and power-domains here. >> > > The driver change was submitted some time ago: > https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@linaro.org/ > > There is already DTS user of it and we expect driver to be resubmitted > at some point. > > What I don't really get is that crypto driver sets bandwidth for > interconnects, not the BAM. Why BAM needs interconnect? Usually you do > not need to initialize some middle paths. Getting the final interconnect > path (e.g. crypto-memory) is enough, because it includes everything in > between. Indeed the interconnect on BAM may be redundant since QCE sets the BW, I'll investigate to understand if it's also necessary on BAM. Neil > > Maybe my review tag was a bit premature... > > Best regards, > Krzysztof >