* [1/2] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
@ 2018-01-06 2:14 Hyun Kwon
0 siblings, 0 replies; 4+ messages in thread
From: Hyun Kwon @ 2018-01-06 2:14 UTC (permalink / raw)
To: dmaengine; +Cc: devicetree, Michal Simek, Hyun Kwon
The ZynqMP includes the DisplayPort subsystem with its own DMA engine
called DPDMA. The DPDMA IP comes with 6 individual channels
(4 for display, 2 for audio). This documentation describes DT bindings
of DPDMA.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
.../bindings/dma/xilinx/xilinx_dpdma.txt | 64 ++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
new file mode 100644
index 0000000..51016d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
@@ -0,0 +1,64 @@
+Device-Tree bindings for Xilinx ZynqMP DP Subsystem DMA
+
+The ZynqMP DisplayPort subsystem handles DMA channel buffer management,
+blending, and audio mixing. The DisplayPort subsystem receives display
+and audio frames from DPDMA and transmits output to the DisplayPort IP core.
+
+Required properties:
+ - compatible: Should be "xlnx,dpdma".
+ - reg: Base address and size of the IP core.
+ - interrupts: Interrupt number.
+ - interrupts-parent: phandle for interrupt controller.
+ - clocks: phandle for AXI clock
+ - clock-names: The identification string, "axi_clk", is always required.
+
+Required child node properties:
+- compatible: Should be one of "xlnx,video0", "xlnx,video1", "xlnx,video2",
+ "xlnx,graphics", "xlnx,audio0", or "xlnx,audio1".
+
+Example:
+
+ xlnx_dpdma: axidpdma@43c10000 {
+ compatible = "xlnx,dpdma";
+ reg = <0x43c10000 0x1000>;
+ interrupts = <0 54 4>;
+ interrupt-parent = <&intc>;
+ clocks = <&clkc 16>;
+ clock-names = "axi_clk";
+
+ #dma-cells = <1>;
+ dma-video0channel {
+ compatible = "xlnx,video0";
+ };
+ dma-video1channel {
+ compatible = "xlnx,video1";
+ };
+ dma-video2channel {
+ compatible = "xlnx,video2";
+ };
+ dma-graphicschannel {
+ compatible = "xlnx,graphics";
+ };
+ dma-audio0channel {
+ compatible = "xlnx,audio0";
+ };
+ dma-audio1channel {
+ compatible = "xlnx,audio1";
+ };
+ };
+
+* DMA client
+
+Required properties:
+- dmas: a list of <[DPDMA device phandle] [Channel ID]> pairs. "Channel ID"
+ is defined as video0 = 0, video1 = 1, video2 = 2, graphics = 3, audio0 = 4,
+ and audio1 = 5.
+
+Example:
+
+ xlnx_drm {
+ ...
+ dmas = <&xlnx_dpdma 3>;
+ dma-names = "dma";
+ ...
+ };
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [1/2] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
@ 2018-01-12 13:28 Vinod Koul
0 siblings, 0 replies; 4+ messages in thread
From: Vinod Koul @ 2018-01-12 13:28 UTC (permalink / raw)
To: Hyun Kwon; +Cc: dmaengine, devicetree, Michal Simek, Rob Herring
On Fri, Jan 05, 2018 at 06:14:07PM -0800, Hyun Kwon wrote:
> The ZynqMP includes the DisplayPort subsystem with its own DMA engine
> called DPDMA. The DPDMA IP comes with 6 individual channels
> (4 for display, 2 for audio). This documentation describes DT bindings
> of DPDMA.
Pls cc DT maintainers on this patch
> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> .../bindings/dma/xilinx/xilinx_dpdma.txt | 64 ++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> new file mode 100644
> index 0000000..51016d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> @@ -0,0 +1,64 @@
> +Device-Tree bindings for Xilinx ZynqMP DP Subsystem DMA
> +
> +The ZynqMP DisplayPort subsystem handles DMA channel buffer management,
> +blending, and audio mixing. The DisplayPort subsystem receives display
> +and audio frames from DPDMA and transmits output to the DisplayPort IP core.
> +
> +Required properties:
> + - compatible: Should be "xlnx,dpdma".
> + - reg: Base address and size of the IP core.
> + - interrupts: Interrupt number.
> + - interrupts-parent: phandle for interrupt controller.
> + - clocks: phandle for AXI clock
> + - clock-names: The identification string, "axi_clk", is always required.
> +
> +Required child node properties:
> +- compatible: Should be one of "xlnx,video0", "xlnx,video1", "xlnx,video2",
> + "xlnx,graphics", "xlnx,audio0", or "xlnx,audio1".
> +
> +Example:
> +
> + xlnx_dpdma: axidpdma@43c10000 {
> + compatible = "xlnx,dpdma";
> + reg = <0x43c10000 0x1000>;
> + interrupts = <0 54 4>;
> + interrupt-parent = <&intc>;
> + clocks = <&clkc 16>;
> + clock-names = "axi_clk";
> +
> + #dma-cells = <1>;
> + dma-video0channel {
> + compatible = "xlnx,video0";
> + };
> + dma-video1channel {
> + compatible = "xlnx,video1";
> + };
> + dma-video2channel {
> + compatible = "xlnx,video2";
> + };
> + dma-graphicschannel {
> + compatible = "xlnx,graphics";
> + };
> + dma-audio0channel {
> + compatible = "xlnx,audio0";
> + };
> + dma-audio1channel {
> + compatible = "xlnx,audio1";
> + };
> + };
> +
> +* DMA client
> +
> +Required properties:
> +- dmas: a list of <[DPDMA device phandle] [Channel ID]> pairs. "Channel ID"
> + is defined as video0 = 0, video1 = 1, video2 = 2, graphics = 3, audio0 = 4,
> + and audio1 = 5.
> +
> +Example:
> +
> + xlnx_drm {
> + ...
> + dmas = <&xlnx_dpdma 3>;
> + dma-names = "dma";
> + ...
> + };
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 4+ messages in thread
* [1/2] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
@ 2018-01-19 19:37 Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2018-01-19 19:37 UTC (permalink / raw)
To: Hyun Kwon; +Cc: dmaengine, devicetree, Michal Simek
On Fri, Jan 05, 2018 at 06:14:07PM -0800, Hyun Kwon wrote:
> The ZynqMP includes the DisplayPort subsystem with its own DMA engine
> called DPDMA. The DPDMA IP comes with 6 individual channels
> (4 for display, 2 for audio). This documentation describes DT bindings
> of DPDMA.
>
> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> .../bindings/dma/xilinx/xilinx_dpdma.txt | 64 ++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> new file mode 100644
> index 0000000..51016d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
Use the compatible string plus .txt for the filename.
> @@ -0,0 +1,64 @@
> +Device-Tree bindings for Xilinx ZynqMP DP Subsystem DMA
> +
> +The ZynqMP DisplayPort subsystem handles DMA channel buffer management,
> +blending, and audio mixing. The DisplayPort subsystem receives display
> +and audio frames from DPDMA and transmits output to the DisplayPort IP core.
> +
> +Required properties:
> + - compatible: Should be "xlnx,dpdma".
xlnx,zynqmp-dpdam
> + - reg: Base address and size of the IP core.
> + - interrupts: Interrupt number.
> + - interrupts-parent: phandle for interrupt controller.
> + - clocks: phandle for AXI clock
> + - clock-names: The identification string, "axi_clk", is always required.
> +
> +Required child node properties:
> +- compatible: Should be one of "xlnx,video0", "xlnx,video1", "xlnx,video2",
> + "xlnx,graphics", "xlnx,audio0", or "xlnx,audio1".
No. This is an abuse of compatible strings.
Why do you need these? You have the DMA channel numbering fixed.
> +
> +Example:
> +
> + xlnx_dpdma: axidpdma@43c10000 {
dma-controller@
> + compatible = "xlnx,dpdma";
> + reg = <0x43c10000 0x1000>;
> + interrupts = <0 54 4>;
> + interrupt-parent = <&intc>;
> + clocks = <&clkc 16>;
> + clock-names = "axi_clk";
> +
> + #dma-cells = <1>;
> + dma-video0channel {
> + compatible = "xlnx,video0";
> + };
> + dma-video1channel {
> + compatible = "xlnx,video1";
> + };
> + dma-video2channel {
> + compatible = "xlnx,video2";
> + };
> + dma-graphicschannel {
> + compatible = "xlnx,graphics";
> + };
> + dma-audio0channel {
> + compatible = "xlnx,audio0";
> + };
> + dma-audio1channel {
> + compatible = "xlnx,audio1";
> + };
> + };
> +
> +* DMA client
> +
> +Required properties:
> +- dmas: a list of <[DPDMA device phandle] [Channel ID]> pairs. "Channel ID"
> + is defined as video0 = 0, video1 = 1, video2 = 2, graphics = 3, audio0 = 4,
> + and audio1 = 5.
> +
> +Example:
> +
> + xlnx_drm {
> + ...
> + dmas = <&xlnx_dpdma 3>;
> + dma-names = "dma";
> + ...
> + };
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
---
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [1/2] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
@ 2018-01-23 17:03 Hyun Kwon
0 siblings, 0 replies; 4+ messages in thread
From: Hyun Kwon @ 2018-01-23 17:03 UTC (permalink / raw)
To: Rob Herring
Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
Michal Simek
Hi Rob,
Thanks for the review.
> -----Original Message-----
> From: dmaengine-owner@vger.kernel.org [mailto:dmaengine-
> owner@vger.kernel.org] On Behalf Of Rob Herring
> Sent: Friday, January 19, 2018 11:38 AM
> To: Hyun Kwon <hyunk@xilinx.com>
> Cc: dmaengine@vger.kernel.org; devicetree@vger.kernel.org; Michal Simek
> <michal.simek@xilinx.com>
> Subject: Re: [PATCH 1/2] dt: bindings: dma: xilinx: dpdma: DT bindings for
> Xilinx DPDMA
>
> On Fri, Jan 05, 2018 at 06:14:07PM -0800, Hyun Kwon wrote:
> > The ZynqMP includes the DisplayPort subsystem with its own DMA
> engine
> > called DPDMA. The DPDMA IP comes with 6 individual channels
> > (4 for display, 2 for audio). This documentation describes DT bindings
> > of DPDMA.
> >
> > Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> > .../bindings/dma/xilinx/xilinx_dpdma.txt | 64
> ++++++++++++++++++++++
> > 1 file changed, 64 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> >
> > diff --git
> a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
> > new file mode 100644
> > index 0000000..51016d8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt
>
> Use the compatible string plus .txt for the filename.
>
> > @@ -0,0 +1,64 @@
> > +Device-Tree bindings for Xilinx ZynqMP DP Subsystem DMA
> > +
> > +The ZynqMP DisplayPort subsystem handles DMA channel buffer
> management,
> > +blending, and audio mixing. The DisplayPort subsystem receives display
> > +and audio frames from DPDMA and transmits output to the DisplayPort
> IP core.
> > +
> > +Required properties:
> > + - compatible: Should be "xlnx,dpdma".
>
> xlnx,zynqmp-dpdam
>
> > + - reg: Base address and size of the IP core.
> > + - interrupts: Interrupt number.
> > + - interrupts-parent: phandle for interrupt controller.
> > + - clocks: phandle for AXI clock
> > + - clock-names: The identification string, "axi_clk", is always required.
> > +
> > +Required child node properties:
> > +- compatible: Should be one of "xlnx,video0", "xlnx,video1",
> "xlnx,video2",
> > + "xlnx,graphics", "xlnx,audio0", or "xlnx,audio1".
>
> No. This is an abuse of compatible strings.
>
> Why do you need these? You have the DMA channel numbering fixed.
>
> > +
> > +Example:
> > +
> > + xlnx_dpdma: axidpdma@43c10000 {
>
> dma-controller@
>
I agree with your comments. Will address in v2.
Thanks,
-hyun
> > + compatible = "xlnx,dpdma";
> > + reg = <0x43c10000 0x1000>;
> > + interrupts = <0 54 4>;
> > + interrupt-parent = <&intc>;
> > + clocks = <&clkc 16>;
> > + clock-names = "axi_clk";
> > +
> > + #dma-cells = <1>;
> > + dma-video0channel {
> > + compatible = "xlnx,video0";
> > + };
> > + dma-video1channel {
> > + compatible = "xlnx,video1";
> > + };
> > + dma-video2channel {
> > + compatible = "xlnx,video2";
> > + };
> > + dma-graphicschannel {
> > + compatible = "xlnx,graphics";
> > + };
> > + dma-audio0channel {
> > + compatible = "xlnx,audio0";
> > + };
> > + dma-audio1channel {
> > + compatible = "xlnx,audio1";
> > + };
> > + };
> > +
> > +* DMA client
> > +
> > +Required properties:
> > +- dmas: a list of <[DPDMA device phandle] [Channel ID]> pairs. "Channel
> ID"
> > + is defined as video0 = 0, video1 = 1, video2 = 2, graphics = 3, audio0 = 4,
> > + and audio1 = 5.
> > +
> > +Example:
> > +
> > + xlnx_drm {
> > + ...
> > + dmas = <&xlnx_dpdma 3>;
> > + dma-names = "dma";
> > + ...
> > + };
> > --
> > 2.7.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
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