* [v4,5/5] imx8mq.dtsi: add the sdma nodes
@ 2019-01-25 2:55 Angus Ainslie
0 siblings, 0 replies; 2+ messages in thread
From: Angus Ainslie @ 2019-01-25 2:55 UTC (permalink / raw)
To: angus
Cc: angus.ainslie, Vinod Koul, dmaengine, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel, linux-kernel,
Lucas Stach, Daniel Baluta
Add the sdma nodes to the base devicetree for the imx8mq
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c0402375e7c1..f0cd3675ead0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -336,6 +336,17 @@
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
status = "disabled";
};
+
+ sdma2: sdma@302c0000 {
+ compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+ reg = <0x302c0000 0x10000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
+ <&clk IMX8MQ_CLK_SDMA2_ROOT>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
};
bus@30400000 { /* AIPS2 */
@@ -370,6 +381,8 @@
clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
<&clk IMX8MQ_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -381,6 +394,8 @@
clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
<&clk IMX8MQ_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -432,6 +447,8 @@
clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
<&clk IMX8MQ_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
+ dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -465,6 +482,17 @@
status = "disabled";
};
+ sdma1: sdma@30bd0000 {
+ compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+ reg = <0x30bd0000 0x10000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
+ <&clk IMX8MQ_CLK_AHB>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [v4,5/5] imx8mq.dtsi: add the sdma nodes
@ 2019-01-25 9:38 Lucas Stach
0 siblings, 0 replies; 2+ messages in thread
From: Lucas Stach @ 2019-01-25 9:38 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: angus.ainslie, Vinod Koul, dmaengine, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel, linux-kernel,
Daniel Baluta
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> Add the sdma nodes to the base devicetree for the imx8mq
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
One nit below, with that fixed:
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
You might need to split this patch out from the series and send it to
Shawn separately after the dmaengine changes have been accepted.
regards,
Lucas
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 28 +++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index c0402375e7c1..f0cd3675ead0 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -336,6 +336,17 @@
> > clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
> > status = "disabled";
> > };
> +
> > > + sdma2: sdma@302c0000 {
> > + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > + reg = <0x302c0000 0x10000>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
> + <&clk IMX8MQ_CLK_SDMA2_ROOT>;
Some spaces to align the second clock reference as in the rest of this
file, please.
> + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
> > + };
> > };
>
> > bus@30400000 { /* AIPS2 */
> @@ -370,6 +381,8 @@
> > clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> > <&clk IMX8MQ_CLK_UART3_ROOT>;
> > clock-names = "ipg", "per";
> > + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
> > + dma-names = "rx", "tx";
> > status = "disabled";
> > };
>
> @@ -381,6 +394,8 @@
> > clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> > <&clk IMX8MQ_CLK_UART2_ROOT>;
> > clock-names = "ipg", "per";
> > + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
> > + dma-names = "rx", "tx";
> > status = "disabled";
> > };
>
> @@ -432,6 +447,8 @@
> > clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> > <&clk IMX8MQ_CLK_UART4_ROOT>;
> > clock-names = "ipg", "per";
> > + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
> > + dma-names = "rx", "tx";
> > status = "disabled";
> > };
>
> @@ -465,6 +482,17 @@
> > status = "disabled";
> > };
>
> > > + sdma1: sdma@30bd0000 {
> > + compatible = "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
> > + reg = <0x30bd0000 0x10000>;
> > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
> > + <&clk IMX8MQ_CLK_AHB>;
> > + clock-names = "ipg", "ahb";
> > + #dma-cells = <3>;
> > + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
> > + };
> +
> > > fec1: ethernet@30be0000 {
> > compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> > reg = <0x30be0000 0x10000>;
^ permalink raw reply [flat|nested] 2+ messages in thread
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