From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v11,1/4] dmaengine: 8250_mtk_dma: add MediaTek uart DMA support From: Long Cheng Message-Id: <1554970806.14150.16.camel@mhfsdcap03> Date: Thu, 11 Apr 2019 16:20:06 +0800 To: Sean Wang Cc: Vinod Koul , Randy Dunlap , Rob Herring , Mark Rutland , Ryder Lee , Nicolas Boichat , Matthias Brugger , Dan Williams , Greg Kroah-Hartman , Jiri Slaby , Sean Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, srv_heupstream , Yingjoe Chen , YT Shen , Zhenbao Liu List-ID: T24gU3VuLCAyMDE5LTAzLTEwIGF0IDE3OjMxIC0wNzAwLCBTZWFuIFdhbmcgd3JvdGU6Cj4gSGks IExvbmcKPiAKPiBMaXN0IHNvbWUgY29tbWVudHMgYXMgdGhlIGJlbG93IGFuZCB0aGlzIHdlZWsg SSB3aWxsIGZpbmQgYSBib2FyZCB0bwo+IHRlc3QgYW5kIHRoZW4gaW1wcm92ZSB0aGUgZHJpdmVy Lgo+IAo+ICAgICAgICAgIFNlYW4KPiAKPiBPbiBXZWQsIE1hciA2LCAyMDE5IGF0IDU6NDUgUE0g TG9uZyBDaGVuZyA8bG9uZy5jaGVuZ0BtZWRpYXRlay5jb20+IHdyb3RlOgo+ID4KPiA+IEluIERN QSBlbmdpbmUgZnJhbWV3b3JrLCBhZGQgODI1MCB1YXJ0IGRtYSB0byBzdXBwb3J0IE1lZGlhVGVr IHVhcnQuCj4gPiBJZiBNZWRpYVRlayB1YXJ0IGVuYWJsZWQoU0VSSUFMXzgyNTBfTVQ2NTc3KSwg YW5kIHdhbnQgdG8gaW1wcm92ZQo+ID4gdGhlIHBlcmZvcm1hbmNlLCBjYW4gZW5hYmxlIHRoZSBm dW5jdGlvbi4KPiA+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBMb25nIENoZW5nIDxsb25nLmNoZW5nQG1l ZGlhdGVrLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvZG1hL21lZGlhdGVrL0tjb25maWcgICAg ICAgICAgfCAgIDExICsKPiA+ICBkcml2ZXJzL2RtYS9tZWRpYXRlay9NYWtlZmlsZSAgICAgICAg IHwgICAgMSArCj4gPiAgZHJpdmVycy9kbWEvbWVkaWF0ZWsvbXRrLXVhcnQtYXBkbWEuYyB8ICA2 NjAgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4gPiAgMyBmaWxlcyBjaGFuZ2Vk LCA2NzIgaW5zZXJ0aW9ucygrKQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2RtYS9t ZWRpYXRlay9tdGstdWFydC1hcGRtYS5jCj4gPgo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1h L21lZGlhdGVrL0tjb25maWcgYi9kcml2ZXJzL2RtYS9tZWRpYXRlay9LY29uZmlnCj4gPiBpbmRl eCA2ODBmYzA1Li5hYzQ5ZWI2IDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9kbWEvbWVkaWF0ZWsv S2NvbmZpZwo+ID4gKysrIGIvZHJpdmVycy9kbWEvbWVkaWF0ZWsvS2NvbmZpZwo+ID4gQEAgLTI0 LDMgKzI0LDE0IEBAIGNvbmZpZyBNVEtfQ1FETUEKPiA+Cj4gPiAgICAgICAgICAgVGhpcyBjb250 cm9sbGVyIHByb3ZpZGVzIHRoZSBjaGFubmVscyB3aGljaCBpcyBkZWRpY2F0ZWQgdG8KPiA+ICAg ICAgICAgICBtZW1vcnktdG8tbWVtb3J5IHRyYW5zZmVyIHRvIG9mZmxvYWQgZnJvbSBDUFUuCj4g PiArCj4gPiArY29uZmlnIE1US19VQVJUX0FQRE1BCj4gPiArICAgICAgIHRyaXN0YXRlICJNZWRp YVRlayBTb0NzIEFQRE1BIHN1cHBvcnQgZm9yIFVBUlQiCj4gPiArICAgICAgIGRlcGVuZHMgb24g T0YgJiYgU0VSSUFMXzgyNTBfTVQ2NTc3Cj4gPiArICAgICAgIHNlbGVjdCBETUFfRU5HSU5FCj4g PiArICAgICAgIHNlbGVjdCBETUFfVklSVFVBTF9DSEFOTkVMUwo+ID4gKyAgICAgICBoZWxwCj4g PiArICAgICAgICAgU3VwcG9ydCBmb3IgdGhlIFVBUlQgRE1BIGVuZ2luZSBmb3VuZCBvbiBNZWRp YVRlayBNVEsgU29Dcy4KPiA+ICsgICAgICAgICBXaGVuIFNFUklBTF84MjUwX01UNjU3NyBpcyBl bmFibGVkLCBhbmQgaWYgeW91IHdhbnQgdG8gdXNlIERNQSwKPiA+ICsgICAgICAgICB5b3UgY2Fu IGVuYWJsZSB0aGUgY29uZmlnLiBUaGUgRE1BIGVuZ2luZSBjYW4gb25seSBiZSB1c2VkCj4gPiAr ICAgICAgICAgd2l0aCBNZWRpYVRlayBTb0NzLgo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1h L21lZGlhdGVrL01ha2VmaWxlIGIvZHJpdmVycy9kbWEvbWVkaWF0ZWsvTWFrZWZpbGUKPiA+IGlu ZGV4IDQxYmIzODEuLjYxYTZkMjkgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL2RtYS9tZWRpYXRl ay9NYWtlZmlsZQo+ID4gKysrIGIvZHJpdmVycy9kbWEvbWVkaWF0ZWsvTWFrZWZpbGUKPiA+IEBA IC0xLDIgKzEsMyBAQAo+ID4gK29iai0kKENPTkZJR19NVEtfVUFSVF9BUERNQSkgKz0gbXRrLXVh cnQtYXBkbWEubwo+ID4gIG9iai0kKENPTkZJR19NVEtfSFNETUEpICs9IG10ay1oc2RtYS5vCj4g PiAgb2JqLSQoQ09ORklHX01US19DUURNQSkgKz0gbXRrLWNxZG1hLm8KPiA+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2RtYS9tZWRpYXRlay9tdGstdWFydC1hcGRtYS5jIGIvZHJpdmVycy9kbWEvbWVk aWF0ZWsvbXRrLXVhcnQtYXBkbWEuYwo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiA+IGluZGV4 IDAwMDAwMDAuLjllZDdhNDkKPiA+IC0tLSAvZGV2L251bGwKPiA+ICsrKyBiL2RyaXZlcnMvZG1h L21lZGlhdGVrL210ay11YXJ0LWFwZG1hLmMKPiA+IEBAIC0wLDAgKzEsNjYwIEBACj4gPiArLy8g U1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKPiA+ICsvKgo+ID4gKyAqIE1lZGlhVGVr IFVhcnQgQVBETUEgZHJpdmVyLgo+ID4gKyAqCj4gPiArICogQ29weXJpZ2h0IChjKSAyMDE4IE1l ZGlhVGVrIEluYy4KPiA+ICsgKiBBdXRob3I6IExvbmcgQ2hlbmcgPGxvbmcuY2hlbmdAbWVkaWF0 ZWsuY29tPgo+ID4gKyAqLwo+ID4gKwo+ID4gKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4KPiA+ICsj aW5jbHVkZSA8bGludXgvZG1hZW5naW5lLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L2RtYS1tYXBw aW5nLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L2Vyci5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9p bml0Lmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L2ludGVycnVwdC5oPgo+ID4gKyNpbmNsdWRlIDxs aW51eC9pb3BvbGwuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgva2VybmVsLmg+Cj4gPiArI2luY2x1 ZGUgPGxpbnV4L2xpc3QuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPiArI2lu Y2x1ZGUgPGxpbnV4L29mX2RldmljZS5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9vZl9kbWEuaD4K PiA+ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+Cj4gPiArI2luY2x1ZGUgPGxp bnV4L3BtX3J1bnRpbWUuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvc2xhYi5oPgo+ID4gKyNpbmNs dWRlIDxsaW51eC9zcGlubG9jay5oPgo+ID4gKwo+ID4gKyNpbmNsdWRlICIuLi92aXJ0LWRtYS5o Igo+ID4gKwo+ID4gKy8qIFRoZSBkZWZhdWx0IG51bWJlciBvZiB2aXJ0dWFsIGNoYW5uZWwgKi8K PiA+ICsjZGVmaW5lIE1US19VQVJUX0FQRE1BX05SX1ZDSEFOUyAgICAgICA4Cj4gPiArCj4gPiAr I2RlZmluZSBWRkZfRU5fQiAgICAgICAgICAgICAgIEJJVCgwKQo+ID4gKyNkZWZpbmUgVkZGX1NU T1BfQiAgICAgICAgICAgICBCSVQoMCkKPiA+ICsjZGVmaW5lIFZGRl9GTFVTSF9CICAgICAgICAg ICAgQklUKDApCj4gPiArI2RlZmluZSBWRkZfNEdfU1VQUE9SVF9CICAgICAgIEJJVCgwKQo+ID4g KyNkZWZpbmUgVkZGX1JYX0lOVF9FTjBfQiAgICAgICBCSVQoMCkgIC8qIHJ4IHZhbGlkIHNpemUg Pj0gIHZmZiB0aHJlICovCj4gPiArI2RlZmluZSBWRkZfUlhfSU5UX0VOMV9CICAgICAgIEJJVCgx KQo+ID4gKyNkZWZpbmUgVkZGX1RYX0lOVF9FTl9CICAgICAgICAgICAgICAgIEJJVCgwKSAgLyog dHggbGVmdCBzaXplID49IHZmZiB0aHJlICovCj4gPiArI2RlZmluZSBWRkZfV0FSTV9SU1RfQiAg ICAgICAgIEJJVCgwKQo+ID4gKyNkZWZpbmUgVkZGX1JYX0lOVF9DTFJfQiAgICAgICAoQklUKDAp IHwgQklUKDEpKQo+ID4gKyNkZWZpbmUgVkZGX1RYX0lOVF9DTFJfQiAgICAgICAwCj4gPiArI2Rl ZmluZSBWRkZfU1RPUF9DTFJfQiAgICAgICAgIDAKPiA+ICsjZGVmaW5lIFZGRl9JTlRfRU5fQ0xS X0IgICAgICAgMAo+ID4gKyNkZWZpbmUgVkZGXzRHX1NVUFBPUlRfQ0xSX0IgICAwCj4gPiArCj4g PiArLyogaW50ZXJydXB0IHRyaWdnZXIgbGV2ZWwgZm9yIHR4ICovCj4gPiArI2RlZmluZSBWRkZf VFhfVEhSRShuKSAgICAgICAgICgobikgKiA3IC8gOCkKPiA+ICsvKiBpbnRlcnJ1cHQgdHJpZ2dl ciBsZXZlbCBmb3IgcnggKi8KPiA+ICsjZGVmaW5lIFZGRl9SWF9USFJFKG4pICAgICAgICAgKChu KSAqIDMgLyA0KQo+ID4gKwo+ID4gKyNkZWZpbmUgVkZGX1JJTkdfU0laRSAgMHhmZmZmVQo+ID4g Ky8qIGludmVydCB0aGlzIGJpdCB3aGVuIHdyYXAgcmluZyBoZWFkIGFnYWluICovCj4gPiArI2Rl ZmluZSBWRkZfUklOR19XUkFQICAweDEwMDAwVQo+ID4gKwo+ID4gKyNkZWZpbmUgVkZGX0lOVF9G TEFHICAgICAgICAgICAweDAwCj4gPiArI2RlZmluZSBWRkZfSU5UX0VOICAgICAgICAgICAgIDB4 MDQKPiA+ICsjZGVmaW5lIFZGRl9FTiAgICAgICAgICAgICAgICAgMHgwOAo+ID4gKyNkZWZpbmUg VkZGX1JTVCAgICAgICAgICAgICAgICAgICAgICAgIDB4MGMKPiA+ICsjZGVmaW5lIFZGRl9TVE9Q ICAgICAgICAgICAgICAgMHgxMAo+ID4gKyNkZWZpbmUgVkZGX0ZMVVNIICAgICAgICAgICAgICAw eDE0Cj4gPiArI2RlZmluZSBWRkZfQUREUiAgICAgICAgICAgICAgIDB4MWMKPiA+ICsjZGVmaW5l IFZGRl9MRU4gICAgICAgICAgICAgICAgICAgICAgICAweDI0Cj4gPiArI2RlZmluZSBWRkZfVEhS RSAgICAgICAgICAgICAgIDB4MjgKPiA+ICsjZGVmaW5lIFZGRl9XUFQgICAgICAgICAgICAgICAg ICAgICAgICAweDJjCj4gPiArI2RlZmluZSBWRkZfUlBUICAgICAgICAgICAgICAgICAgICAgICAg MHgzMAo+ID4gKy8qIFRYOiB0aGUgYnVmZmVyIHNpemUgSFcgY2FuIHJlYWQuIFJYOiB0aGUgYnVm ZmVyIHNpemUgU1cgY2FuIHJlYWQuICovCj4gPiArI2RlZmluZSBWRkZfVkFMSURfU0laRSAgICAg ICAgIDB4M2MKPiA+ICsvKiBUWDogdGhlIGJ1ZmZlciBzaXplIFNXIGNhbiB3cml0ZS4gUlg6IHRo ZSBidWZmZXIgc2l6ZSBIVyBjYW4gd3JpdGUuICovCj4gPiArI2RlZmluZSBWRkZfTEVGVF9TSVpF ICAgICAgICAgIDB4NDAKPiA+ICsjZGVmaW5lIFZGRl9ERUJVR19TVEFUVVMgICAgICAgMHg1MAo+ ID4gKyNkZWZpbmUgVkZGXzRHX1NVUFBPUlQgICAgICAgICAweDU0Cj4gPiArCj4gPiArc3RydWN0 IG10a191YXJ0X2FwZG1hZGV2IHsKPiA+ICsgICAgICAgc3RydWN0IGRtYV9kZXZpY2UgZGRldjsK PiA+ICsgICAgICAgc3RydWN0IGNsayAqY2xrOwo+ID4gKyAgICAgICBib29sIHN1cHBvcnRfMzNi aXRzOwo+ID4gKyAgICAgICB1bnNpZ25lZCBpbnQgZG1hX3JlcXVlc3RzOwo+ID4gKyAgICAgICB1 bnNpZ25lZCBpbnQgKmRtYV9pcnE7Cj4gPiArfTsKPiA+ICsKPiA+ICtzdHJ1Y3QgbXRrX3VhcnRf YXBkbWFfZGVzYyB7Cj4gPiArICAgICAgIHN0cnVjdCB2aXJ0X2RtYV9kZXNjIHZkOwo+ID4gKwo+ ID4gKyAgICAgICB1bnNpZ25lZCBpbnQgYXZhaWxfbGVuOwo+ID4gK307Cj4gPiArCj4gPiArc3Ry dWN0IG10a19jaGFuIHsKPiA+ICsgICAgICAgc3RydWN0IHZpcnRfZG1hX2NoYW4gdmM7Cj4gPiAr ICAgICAgIHN0cnVjdCBkbWFfc2xhdmVfY29uZmlnIGNmZzsKPiA+ICsgICAgICAgdm9pZCBfX2lv bWVtICpiYXNlOwo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX3VhcnRfYXBkbWFfZGVzYyAqZGVzYzsK PiA+ICsKPiA+ICsgICAgICAgZW51bSBkbWFfdHJhbnNmZXJfZGlyZWN0aW9uIGRpcjsKPiA+ICsK PiA+ICsgICAgICAgYm9vbCByZXF1ZXN0ZWQ7Cj4gPiArCj4gPiArICAgICAgIHVuc2lnbmVkIGlu dCByeF9zdGF0dXM7Cj4gPiArfTsKPiA+ICsKPiA+ICtzdGF0aWMgaW5saW5lIHN0cnVjdCBtdGtf dWFydF9hcGRtYWRldiAqCj4gPiArdG9fbXRrX3VhcnRfYXBkbWFfZGV2KHN0cnVjdCBkbWFfZGV2 aWNlICpkKQo+ID4gK3sKPiA+ICsgICAgICAgcmV0dXJuIGNvbnRhaW5lcl9vZihkLCBzdHJ1Y3Qg bXRrX3VhcnRfYXBkbWFkZXYsIGRkZXYpOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW5saW5l IHN0cnVjdCBtdGtfY2hhbiAqdG9fbXRrX3VhcnRfYXBkbWFfY2hhbihzdHJ1Y3QgZG1hX2NoYW4g KmMpCj4gPiArewo+ID4gKyAgICAgICByZXR1cm4gY29udGFpbmVyX29mKGMsIHN0cnVjdCBtdGtf Y2hhbiwgdmMuY2hhbik7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbmxpbmUgc3RydWN0IG10 a191YXJ0X2FwZG1hX2Rlc2MgKnRvX210a191YXJ0X2FwZG1hX2Rlc2MKPiA+ICsgICAgICAgKHN0 cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqdCkKPiA+ICt7Cj4gPiArICAgICAgIHJldHVy biBjb250YWluZXJfb2YodCwgc3RydWN0IG10a191YXJ0X2FwZG1hX2Rlc2MsIHZkLnR4KTsKPiA+ ICt9Cj4gPiArCj4gPiArc3RhdGljIHZvaWQgbXRrX3VhcnRfYXBkbWFfd3JpdGUoc3RydWN0IG10 a19jaGFuICpjLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHVuc2lnbmVkIGlu dCByZWcsIHVuc2lnbmVkIGludCB2YWwpCj4gPiArewo+ID4gKyAgICAgICB3cml0ZWwodmFsLCBj LT5iYXNlICsgcmVnKTsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHVuc2lnbmVkIGludCBtdGtf dWFydF9hcGRtYV9yZWFkKHN0cnVjdCBtdGtfY2hhbiAqYywgdW5zaWduZWQgaW50IHJlZykKPiA+ ICt7Cj4gPiArICAgICAgIHJldHVybiByZWFkbChjLT5iYXNlICsgcmVnKTsKPiA+ICt9Cj4gPiAr Cj4gPiArc3RhdGljIHZvaWQgbXRrX3VhcnRfYXBkbWFfZGVzY19mcmVlKHN0cnVjdCB2aXJ0X2Rt YV9kZXNjICp2ZCkKPiA+ICt7Cj4gPiArICAgICAgIHN0cnVjdCBkbWFfY2hhbiAqY2hhbiA9IHZk LT50eC5jaGFuOwo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX2NoYW4gKmMgPSB0b19tdGtfdWFydF9h cGRtYV9jaGFuKGNoYW4pOwo+ID4gKwo+ID4gKyAgICAgICBrZnJlZShjLT5kZXNjKTsKPiA+ICt9 Cj4gPiArCj4gPiArc3RhdGljIHZvaWQgbXRrX3VhcnRfYXBkbWFfc3RhcnRfdHgoc3RydWN0IG10 a19jaGFuICpjKQo+ID4gK3sKPiA+ICsgICAgICAgdW5zaWduZWQgaW50IGxlbiwgc2VuZCwgbGVm dCwgd3B0LCBkX3dwdCwgdG1wOwo+ID4gKyAgICAgICBpbnQgcmV0Owo+ID4gKwo+ID4gKyAgICAg ICBsZWZ0ID0gbXRrX3VhcnRfYXBkbWFfcmVhZChjLCBWRkZfTEVGVF9TSVpFKTsKPiA+ICsgICAg ICAgaWYgKCFsZWZ0KSB7Cj4gPiArICAgICAgICAgICAgICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUo YywgVkZGX0lOVF9FTiwgVkZGX1RYX0lOVF9FTl9CKTsKPiA+ICsgICAgICAgICAgICAgICByZXR1 cm47Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgLyogV2FpdCAxc2VjIGZvciBmbHVz aCwgY2FuJ3Qgc2xlZXAgKi8KPiA+ICsgICAgICAgcmV0ID0gcmVhZHhfcG9sbF90aW1lb3V0KHJl YWRsLCBjLT5iYXNlICsgVkZGX0ZMVVNILCB0bXAsCj4gPiArICAgICAgICAgICAgICAgICAgICAg ICB0bXAgIT0gVkZGX0ZMVVNIX0IsIDAsIDEwMDAwMDApOwo+IAo+IEl0IGlzIHJlYWxseSBub3Qg YSBnb29kIGlkZWEgdGhhdCBwb2xsaW5nIHVwIHRvIDEgc2Vjb25kIGluIGFuCj4gaW50ZXJydXB0 IGNvbnRleHQuCj4gCgpJIHdpbGwgbW9kaWZ5IGl0IGluIG5leHQgdmVyc2lvbi4KCj4gPiArICAg ICAgIGlmIChyZXQpCj4gPiArICAgICAgICAgICAgICAgZGV2X3dhcm4oYy0+dmMuY2hhbi5kZXZp Y2UtPmRldiwgInR4OiBmYWlsLCBkZWJ1Zz0weCV4XG4iLAo+ID4gKyAgICAgICAgICAgICAgICAg ICAgICAgbXRrX3VhcnRfYXBkbWFfcmVhZChjLCBWRkZfREVCVUdfU1RBVFVTKSk7Cj4gPiArCj4g PiArICAgICAgIHNlbmQgPSBtaW5fdCh1bnNpZ25lZCBpbnQsIGxlZnQsIGMtPmRlc2MtPmF2YWls X2xlbik7Cj4gPiArICAgICAgIHdwdCA9IG10a191YXJ0X2FwZG1hX3JlYWQoYywgVkZGX1dQVCk7 Cj4gPiArICAgICAgIGxlbiA9IGMtPmNmZy5kc3RfcG9ydF93aW5kb3dfc2l6ZTsKPiA+ICsKPiA+ ICsgICAgICAgZF93cHQgPSB3cHQgKyBzZW5kOwo+ID4gKyAgICAgICBpZiAoKGRfd3B0ICYgVkZG X1JJTkdfU0laRSkgPj0gbGVuKSB7Cj4gCj4gSSBhbSBjb25mdXNlZCB3aGF0IHNpemUgb2YgVkZG IGlzLiAgRWl0aGVyIFZGRl9SSU5HX1NJWkUgb3IKPiBjLT5jZmcuZHN0X3BvcnRfd2luZG93X3Np emU/Cj4gCgpWRkZfUlJJTkdfU0laRSBpcyBtYXggbGVuZ3RoIHRoYXQgSFcgY2FuIHN1cHBvcnQu VGhlCmMtPmNmZy5kc3RfcG9ydF93aW5kb3dfc2l6ZSBpcyBhY3R1YWwgbGVuZ3RoLiAKCj4gPiAr ICAgICAgICAgICAgICAgZF93cHQgPSBkX3dwdCAtIGxlbjsKPiA+ICsgICAgICAgICAgICAgICBk X3dwdCA9IGRfd3B0IF4gVkZGX1JJTkdfV1JBUDsKPiA+ICsgICAgICAgfQo+ID4gKyAgICAgICBt dGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfV1BULCBkX3dwdCk7Cj4gPiArCj4gPiArICAgICAg IGMtPmRlc2MtPmF2YWlsX2xlbiAtPSBzZW5kOwo+ID4gKwo+ID4gKyAgICAgICBtdGtfdWFydF9h cGRtYV93cml0ZShjLCBWRkZfSU5UX0VOLCBWRkZfVFhfSU5UX0VOX0IpOwo+IAo+IFdoeSBzaG91 bGQgd2UgbmVlZCB0byBwcm9ncmFtIGludGVycnVwdCBlbmFibGVkIGJpdCBhZ2Fpbj8KCkhXIHJl cXVlc3QuIHRoZSBzdGVwIGlzIG11c3QuCgo+IAo+ID4gKyAgICAgICBpZiAobXRrX3VhcnRfYXBk bWFfcmVhZChjLCBWRkZfRkxVU0gpID09IDBVKQo+ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0 X2FwZG1hX3dyaXRlKGMsIFZGRl9GTFVTSCwgVkZGX0ZMVVNIX0IpOwo+ID4gK30KPiA+ICsKPiA+ ICtzdGF0aWMgdm9pZCBtdGtfdWFydF9hcGRtYV9zdGFydF9yeChzdHJ1Y3QgbXRrX2NoYW4gKmMp Cj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX3VhcnRfYXBkbWFfZGVzYyAqZCA9IGMtPmRl c2M7Cj4gPiArICAgICAgIHVuc2lnbmVkIGludCBsZW4sIHdnLCByZzsKPiA+ICsgICAgICAgaW50 IGNudDsKPiA+ICsKPiA+ICsgICAgICAgaWYgKChtdGtfdWFydF9hcGRtYV9yZWFkKGMsIFZGRl9W QUxJRF9TSVpFKSA9PSAwVSkgfHwKPiA+ICsgICAgICAgICAgICAgICAhZCB8fCAhdmNoYW5fbmV4 dF9kZXNjKCZjLT52YykpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuOwo+IAo+IElmIHRoZSBj dXJyZW50IGRlc2NyaXB0b3IgaXMgbm90IGF2YWlsYWJsZSwgdGhlIGhhcmR3YXJlIHNob3VsZCBi ZQo+IGlkbGUgb3Igc3RvcHBlZC4gc28gSSB0aGluayB0aGUgY29uZGl0aW9uIGNhbiBiZSByZW1v dmVkIG9yIHRoZXJlIGlzCj4gc29tZXdoZXJlIHlvdXIgaGFuZGxlIGRlc2NyaXB0b3JzIGluY29y cmVjdGx5LgoKSSB3aWxsIG1vZGlmeSBpdCBpbiBuZXh0IHZlcnNpb24uCgo+IAo+ID4gKwo+ID4g KyAgICAgICBsZW4gPSBjLT5jZmcuc3JjX3BvcnRfd2luZG93X3NpemU7Cj4gPiArICAgICAgIHJn ID0gbXRrX3VhcnRfYXBkbWFfcmVhZChjLCBWRkZfUlBUKTsKPiA+ICsgICAgICAgd2cgPSBtdGtf dWFydF9hcGRtYV9yZWFkKGMsIFZGRl9XUFQpOwo+ID4gKyAgICAgICBjbnQgPSAod2cgJiBWRkZf UklOR19TSVpFKSAtIChyZyAmIFZGRl9SSU5HX1NJWkUpOwo+IAo+IElzIGl0IHBvc3NpYmxlIHRo YXQgcmcgYW5kIHdnIHdvdWxkIGJlIGdyZWF0ZXIgdGhhbiBWRkZfUklOR19TSVpFPwo+IAoKTm8u Cgo+ID4gKyAgICAgICAvKgo+ID4gKyAgICAgICAgKiBUaGUgYnVmZmVyIGlzIHJpbmcgYnVmZmVy LiBJZiB3cmFwIGJpdCBkaWZmZXJlbnQsCj4gPiArICAgICAgICAqIHJlcHJlc2VudHMgdGhlIHN0 YXJ0IG9mIHRoZSBuZXh0IGN5Y2xlIGZvciBXUFQKPiA+ICsgICAgICAgICovCj4gPiArICAgICAg IGlmICgocmcgXiB3ZykgJiBWRkZfUklOR19XUkFQKQo+ID4gKyAgICAgICAgICAgICAgIGNudCAr PSBsZW47Cj4gCj4gQWdhaW4sIEkgYW0gY29uZnVzZWQgd2hhdCBzaXplIG9mIFZGRiBpcy4gIEVp dGhlciBWRkZfUklOR19TSVpFIG9yCj4gYy0+Y2ZnLmRzdF9wb3J0X3dpbmRvd19zaXplPwo+IAo+ ID4gKwo+ID4gKyAgICAgICBjLT5yeF9zdGF0dXMgPSBkLT5hdmFpbF9sZW4gLSBjbnQ7Cj4gPiAr ICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9SUFQsIHdnKTsKPiA+ICsKPiA+ICsg ICAgICAgbGlzdF9kZWwoJmQtPnZkLm5vZGUpOwo+ID4gKyAgICAgICB2Y2hhbl9jb29raWVfY29t cGxldGUoJmQtPnZkKTsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIGlycXJldHVybl90IG10a191 YXJ0X2FwZG1hX2lycV9oYW5kbGVyKGludCBpcnEsIHZvaWQgKmRldl9pZCkKPiA+ICt7Cj4gPiAr ICAgICAgIHN0cnVjdCBkbWFfY2hhbiAqY2hhbiA9IChzdHJ1Y3QgZG1hX2NoYW4gKilkZXZfaWQ7 Cj4gPiArICAgICAgIHN0cnVjdCBtdGtfY2hhbiAqYyA9IHRvX210a191YXJ0X2FwZG1hX2NoYW4o Y2hhbik7Cj4gPiArICAgICAgIHN0cnVjdCBtdGtfdWFydF9hcGRtYV9kZXNjICpkOwo+ID4gKyAg ICAgICB1bnNpZ25lZCBsb25nIGZsYWdzOwo+ID4gKwo+ID4gKyAgICAgICBzcGluX2xvY2tfaXJx c2F2ZSgmYy0+dmMubG9jaywgZmxhZ3MpOwo+ID4gKyAgICAgICBpZiAoYy0+ZGlyID09IERNQV9E RVZfVE9fTUVNKSB7Cj4gPiArICAgICAgICAgICAgICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUoYywg VkZGX0lOVF9GTEFHLCBWRkZfUlhfSU5UX0NMUl9CKTsKPiA+ICsgICAgICAgICAgICAgICBtdGtf dWFydF9hcGRtYV9zdGFydF9yeChjKTsKPiA+ICsgICAgICAgfSBlbHNlIGlmIChjLT5kaXIgPT0g RE1BX01FTV9UT19ERVYpIHsKPiA+ICsgICAgICAgICAgICAgICBkID0gYy0+ZGVzYzsKPiA+ICsK PiA+ICsgICAgICAgICAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfSU5UX0ZMQUcs IFZGRl9UWF9JTlRfQ0xSX0IpOwo+ID4gKwo+ID4gKyAgICAgICAgICAgICAgIGlmIChkLT5hdmFp bF9sZW4gIT0gMFUpIHsKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1h X3N0YXJ0X3R4KGMpOwo+ID4gKyAgICAgICAgICAgICAgIH0gZWxzZSB7Cj4gPiArICAgICAgICAg ICAgICAgICAgICAgICBsaXN0X2RlbCgmZC0+dmQubm9kZSk7Cj4gPiArICAgICAgICAgICAgICAg ICAgICAgICB2Y2hhbl9jb29raWVfY29tcGxldGUoJmQtPnZkKTsKPiA+ICsgICAgICAgICAgICAg ICB9Cj4gPiArICAgICAgIH0KPiA+ICsgICAgICAgc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmYy0+ dmMubG9jaywgZmxhZ3MpOwo+ID4gKwo+ID4gKyAgICAgICByZXR1cm4gSVJRX0hBTkRMRUQ7Cj4g PiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgbXRrX3VhcnRfYXBkbWFfYWxsb2NfY2hhbl9yZXNv dXJjZXMoc3RydWN0IGRtYV9jaGFuICpjaGFuKQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IG10 a191YXJ0X2FwZG1hZGV2ICptdGtkID0gdG9fbXRrX3VhcnRfYXBkbWFfZGV2KGNoYW4tPmRldmlj ZSk7Cj4gPiArICAgICAgIHN0cnVjdCBtdGtfY2hhbiAqYyA9IHRvX210a191YXJ0X2FwZG1hX2No YW4oY2hhbik7Cj4gPiArICAgICAgIHVuc2lnbmVkIGludCB0bXA7Cj4gPiArICAgICAgIGludCBy ZXQ7Cj4gPiArCj4gPiArICAgICAgIHBtX3J1bnRpbWVfZ2V0X3N5bmMobXRrZC0+ZGRldi5kZXYp Owo+IAo+IEFkZCBhbiBlcnJvciBoYW5kbGluZywgc29tZXRoaW5nIGxpa2UKPiAKPiBlcnIgPSBw bV9ydW50aW1lX2dldF9zeW5jKG10a2QtPmRkZXYuZGV2KTsKPiBpZiAoZXJyIDwgMCkgewo+IHBt X3J1bnRpbWVfcHV0X25vaWRsZShkZXYpOwo+IC4uLgo+IH0KPiAKCkkgd2lsbCBtb2RpZnkgaXQg aW4gbmV4dCB2ZXJzaW9uLgoKPiA+ICsKPiA+ICsgICAgICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUo YywgVkZGX0FERFIsIDApOwo+ID4gKyAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZf VEhSRSwgMCk7Cj4gPiArICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9MRU4sIDAp Owo+ID4gKyAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfUlNULCBWRkZfV0FSTV9S U1RfQik7Cj4gPiArCj4gPiArICAgICAgIHJldCA9IHJlYWR4X3BvbGxfdGltZW91dChyZWFkbCwg Yy0+YmFzZSArIFZGRl9FTiwgdG1wLCAhdG1wLCAxMCwgMTAwKTsKPiA+ICsgICAgICAgaWYgKHJl dCkgewo+ID4gKyAgICAgICAgICAgICAgIGRldl9lcnIoY2hhbi0+ZGV2aWNlLT5kZXYsICJkbWEg cmVzZXQ6IGZhaWwsIHRpbWVvdXRcbiIpOwo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiByZXQ7 Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgaWYgKCFjLT5yZXF1ZXN0ZWQpIHsKPiA+ ICsgICAgICAgICAgICAgICBjLT5yZXF1ZXN0ZWQgPSB0cnVlOwo+IAo+IFRoZSB2YXJpYWJsZSBj LT5yZXF1ZXN0ZWQgY2FuIGJlIHNhdmVkIHNpbmNlIHRoZSBzYW1lIGNoYW5uZWwKPiBzaG91bGRu J3QgYmUgcmVxdWVzdGVkIG1vcmUgb25lIHRpbWUKPiAKSSB3aWxsIG1vZGlmeSBpdCBpbiBuZXh0 IHZlcnNpb24uCgo+ID4gKyAgICAgICAgICAgICAgIHJldCA9IHJlcXVlc3RfaXJxKG10a2QtPmRt YV9pcnFbY2hhbi0+Y2hhbl9pZF0sCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgbXRrX3VhcnRfYXBkbWFfaXJxX2hhbmRsZXIsIElSUUZfVFJJR0dFUl9OT05FLAo+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIEtCVUlMRF9NT0ROQU1FLCBjaGFuKTsKPiA+ ICsgICAgICAgICAgICAgICBpZiAocmV0IDwgMCkgewo+ID4gKyAgICAgICAgICAgICAgICAgICAg ICAgZGV2X2VycihjaGFuLT5kZXZpY2UtPmRldiwgIkNhbid0IHJlcXVlc3QgZG1hIElSUVxuIik7 Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICByZXR1cm4gLUVJTlZBTDsKPiA+ICsgICAgICAg ICAgICAgICB9Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgaWYgKG10a2QtPnN1cHBv cnRfMzNiaXRzKQo+ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZG Rl80R19TVVBQT1JULCBWRkZfNEdfU1VQUE9SVF9DTFJfQik7Cj4gPiArCj4gPiArICAgICAgIHJl dHVybiByZXQ7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyB2b2lkIG10a191YXJ0X2FwZG1hX2Zy ZWVfY2hhbl9yZXNvdXJjZXMoc3RydWN0IGRtYV9jaGFuICpjaGFuKQo+ID4gK3sKPiA+ICsgICAg ICAgc3RydWN0IG10a191YXJ0X2FwZG1hZGV2ICptdGtkID0gdG9fbXRrX3VhcnRfYXBkbWFfZGV2 KGNoYW4tPmRldmljZSk7Cj4gPiArICAgICAgIHN0cnVjdCBtdGtfY2hhbiAqYyA9IHRvX210a191 YXJ0X2FwZG1hX2NoYW4oY2hhbik7Cj4gPiArCj4gPiArICAgICAgIGlmIChjLT5yZXF1ZXN0ZWQp IHsKPiAKPiBkaXR0byBhcyB0aGUgYWJvdmUKCkkgd2lsbCBtb2RpZnkgaXQgaW4gbmV4dCB2ZXJz aW9uLgo+IAo+ID4gKyAgICAgICAgICAgICAgIGMtPnJlcXVlc3RlZCA9IGZhbHNlOwo+ID4gKyAg ICAgICAgICAgICAgIGZyZWVfaXJxKG10a2QtPmRtYV9pcnFbY2hhbi0+Y2hhbl9pZF0sIGNoYW4p Owo+ID4gKyAgICAgICB9Cj4gPiArCj4gPiArICAgICAgIHRhc2tsZXRfa2lsbCgmYy0+dmMudGFz ayk7Cj4gPiArCj4gPiArICAgICAgIHZjaGFuX2ZyZWVfY2hhbl9yZXNvdXJjZXMoJmMtPnZjKTsK PiA+ICsKPiA+ICsgICAgICAgcG1fcnVudGltZV9wdXRfc3luYyhtdGtkLT5kZGV2LmRldik7Cj4g PiArfQo+ID4gKwo+ID4gK3N0YXRpYyBlbnVtIGRtYV9zdGF0dXMgbXRrX3VhcnRfYXBkbWFfdHhf c3RhdHVzKHN0cnVjdCBkbWFfY2hhbiAqY2hhbiwKPiA+ICsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgZG1hX2Nvb2tpZV90IGNvb2tpZSwKPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgc3RydWN0IGRtYV90eF9zdGF0ZSAqdHhzdGF0ZSkK PiA+ICt7Cj4gPiArICAgICAgIHN0cnVjdCBtdGtfY2hhbiAqYyA9IHRvX210a191YXJ0X2FwZG1h X2NoYW4oY2hhbik7Cj4gPiArICAgICAgIGVudW0gZG1hX3N0YXR1cyByZXQ7Cj4gPiArCj4gPiAr ICAgICAgIHJldCA9IGRtYV9jb29raWVfc3RhdHVzKGNoYW4sIGNvb2tpZSwgdHhzdGF0ZSk7Cj4g PiArCj4gPiArICAgICAgIGRtYV9zZXRfcmVzaWR1ZSh0eHN0YXRlLCBjLT5yeF9zdGF0dXMpOwo+ ID4gKwo+IAo+IFRoZSBoYW5kbGluZyBpcyBub3QgZW5vdWdoLiBZb3Ugc2hvdWxkIGdldCB0aGUg ZGVzY3JpcHRvcgo+IGNvcnJlc3BvbmRpbmcgdG8gdGhlIGNvb2tpZSBhbmQgdGhlbiBjYWxjdWxh dGUgYW5kIHJldHVybiB0aGUKPiAtPnR4X3N0YXR1cyBieSB0aGUgZGVzY3JpcHRvcgo+IAoKQmVj YXVzZSBVQVJUIGNhbid0IGdldCBhbnkgaW50ZXJydXB0IGV4Y2VwdCBETUEgaW50ZXJydXB0LiBT byBpbiBBUERNQSwKbmVlZCBub3RpZnkgVUFSVCB0byBnZXQgZGF0YS4gQW5kIHRoZW4gZGVzY3Jp cHRvciB3aWxsIGJlIHJlbGVhc2VkLiBTbwpOZWVkIGtlZXAgdGhlIHNvbHV0aW9uLgoKPiA+ICsg ICAgICAgcmV0dXJuIHJldDsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIHZvaWQgbXRrX3VhcnRf YXBkbWFfY29uZmlnX3dyaXRlKHN0cnVjdCBkbWFfY2hhbiAqY2hhbiwKPiA+ICsgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgZG1hX3NsYXZlX2NvbmZpZyAqY2ZnLAo+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIGVudW0gZG1hX3RyYW5zZmVyX2RpcmVjdGlvbiBk aXIpCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX2NoYW4gKmMgPSB0b19tdGtfdWFydF9h cGRtYV9jaGFuKGNoYW4pOwo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX3VhcnRfYXBkbWFkZXYgKm10 a2QgPQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB0b19tdGtfdWFydF9hcGRt YV9kZXYoYy0+dmMuY2hhbi5kZXZpY2UpOwo+ID4gKyAgICAgICB1bnNpZ25lZCBpbnQgdG1wOwo+ ID4gKwo+ID4gKyAgICAgICBpZiAobXRrX3VhcnRfYXBkbWFfcmVhZChjLCBWRkZfRU4pID09IFZG Rl9FTl9CKQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybjsKPiA+ICsKPiA+ICsgICAgICAgYy0+ ZGlyID0gZGlyOwo+IAo+IFRoZSBkaXJlY3Rpb24gaXMgZml4ZWQgYnkgdGhlIGRldmljZSwgSSBk b24ndCB0aGluayBpdCBpcyByZXF1aXJlZCB0bwo+IGtlZXAgaXQgaW4gYSBzb2Z0d2FyZSBzdGF0 ZS4KCk5lZWQgc2F2ZSBpdC4gQmVjYXVzZSBSWCBhbmQgVFggaXNuJ3QgYWxsIHNhbWUuCgo+IAo+ ID4gKwo+ID4gKyAgICAgICBpZiAoZGlyID09IERNQV9ERVZfVE9fTUVNKSB7Cj4gPiArICAgICAg ICAgICAgICAgdG1wID0gY2ZnLT5zcmNfcG9ydF93aW5kb3dfc2l6ZTsKPiA+ICsKPiA+ICsgICAg ICAgICAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfQUREUiwgY2ZnLT5zcmNfYWRk cik7Cj4gCj4gVGhhdCBpcyB3cm9uZy4gLT5zcmNfYWRkciBpcyB0aGUgcGh5c2ljYWwgYWRkcmVz cyB3aGVyZSBETUEgc2xhdmUgZGF0YQo+IHNob3VsZCBiZSByZWFkIChSWCksICBub3QgdGhlIG1l bW9yeSBhZGRyZXNzLgo+IAo+IFlvdSBzaG91bGQgcHJvZ3JhbSB0aGUgcmVnaXN0ZXIgVkZGX0FE RFIgYW5kIFZGRl9MRU4gYnkgc2cgYWRkcmVzcyBhbmQKPiBsZW5ndGggZnJvbSBkZXZpY2VfcHJl cF9zbGF2ZV9zZy4KCkkgd2lsbCBtb2RpZnkgaXQgaW4gbmV4dCB2ZXJzaW9uLgo+IAo+ID4gKyAg ICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9MRU4sIHRtcCk7Cj4gPiAr ICAgICAgICAgICAgICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUoYywgVkZGX1RIUkUsIFZGRl9SWF9U SFJFKHRtcCkpOwo+ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZG Rl9JTlRfRU4sCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFZGRl9SWF9JTlRf RU4wX0IgfCBWRkZfUlhfSU5UX0VOMV9CKTsKPiA+ICsgICAgICAgICAgICAgICBtdGtfdWFydF9h cGRtYV93cml0ZShjLCBWRkZfUlBULCAwKTsKPiA+ICsgICAgICAgICAgICAgICBtdGtfdWFydF9h cGRtYV93cml0ZShjLCBWRkZfSU5UX0ZMQUcsIFZGRl9SWF9JTlRfQ0xSX0IpOwo+ID4gKyAgICAg ICB9IGVsc2UgaWYgKGRpciA9PSBETUFfTUVNX1RPX0RFVikgICAgICAgewo+ID4gKyAgICAgICAg ICAgICAgIHRtcCA9IGNmZy0+ZHN0X3BvcnRfd2luZG93X3NpemU7Cj4gPiArCj4gPiArICAgICAg ICAgICAgICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUoYywgVkZGX0FERFIsIGNmZy0+ZHN0X2FkZHIp Owo+IAo+IFRoYXQgaXMgYWxzbyB3cm9uZy4gc3RfYWRkcjogdGhpcyBpcyB0aGUgcGh5c2ljYWwg YWRkcmVzcyB3aGVyZSBETUEKPiBzbGF2ZSBkYXRhIHNob3VsZCBiZSB3cml0dGVuIChUWCksIG5v dCB0aGUgbWVtb3J5IGFkZHJlc3Mgc2ltaWxhciB0bwo+IHRoZSBhYm92ZSBleHBsYW5hdGlvbi4K Ckkgd2lsbCBtb2RpZnkgaXQgaW4gbmV4dCB2ZXJzaW9uLgo+IAo+ID4gKyAgICAgICAgICAgICAg IG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9MRU4sIHRtcCk7Cj4gPiArICAgICAgICAgICAg ICAgbXRrX3VhcnRfYXBkbWFfd3JpdGUoYywgVkZGX1RIUkUsIFZGRl9UWF9USFJFKHRtcCkpOwo+ ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9XUFQsIDApOwo+ ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9JTlRfRkxBRywg VkZGX1RYX0lOVF9DTFJfQik7Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgbXRrX3Vh cnRfYXBkbWFfd3JpdGUoYywgVkZGX0VOLCBWRkZfRU5fQik7Cj4gPiArCj4gPiArICAgICAgIGlm IChtdGtkLT5zdXBwb3J0XzMzYml0cykKPiA+ICsgICAgICAgICAgICAgICBtdGtfdWFydF9hcGRt YV93cml0ZShjLCBWRkZfNEdfU1VQUE9SVCwgVkZGXzRHX1NVUFBPUlRfQik7Cj4gPiArCj4gPiAr ICAgICAgIGlmIChtdGtfdWFydF9hcGRtYV9yZWFkKGMsIFZGRl9FTikgIT0gVkZGX0VOX0IpCj4g PiArICAgICAgICAgICAgICAgZGV2X2VycihjaGFuLT5kZXZpY2UtPmRldiwgImRpclslZF0gZmFp bFxuIiwgZGlyKTsKPiA+ICt9Cj4gPiArCj4gPiArLyoKPiA+ICsgKiBkbWFlbmdpbmVfcHJlcF9z bGF2ZV9zaW5nbGUgd2lsbCBjYWxsIHRoZSBmdW5jdGlvbi4gYW5kIHNnbGVuIGlzIDEuCj4gPiAr ICogODI1MCB1YXJ0IHVzaW5nIG9uZSByaW5nIGJ1ZmZlciwgYW5kIGRlYWwgd2l0aCBvbmUgc2cu Cj4gPiArICovCj4gPiArc3RhdGljIHN0cnVjdCBkbWFfYXN5bmNfdHhfZGVzY3JpcHRvciAqbXRr X3VhcnRfYXBkbWFfcHJlcF9zbGF2ZV9zZwo+ID4gKyAgICAgICAoc3RydWN0IGRtYV9jaGFuICpj aGFuLCBzdHJ1Y3Qgc2NhdHRlcmxpc3QgKnNnbCwKPiA+ICsgICAgICAgdW5zaWduZWQgaW50IHNn bGVuLCBlbnVtIGRtYV90cmFuc2Zlcl9kaXJlY3Rpb24gZGlyLAo+ID4gKyAgICAgICB1bnNpZ25l ZCBsb25nIHR4X2ZsYWdzLCB2b2lkICpjb250ZXh0KQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0 IG10a19jaGFuICpjID0gdG9fbXRrX3VhcnRfYXBkbWFfY2hhbihjaGFuKTsKPiA+ICsgICAgICAg c3RydWN0IG10a191YXJ0X2FwZG1hX2Rlc2MgKmQ7Cj4gPiArCj4gPiArICAgICAgIGlmICghaXNf c2xhdmVfZGlyZWN0aW9uKGRpcikpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIE5VTEw7Cj4g PiArCj4gPiArICAgICAgIG10a191YXJ0X2FwZG1hX2NvbmZpZ193cml0ZShjaGFuLCAmYy0+Y2Zn LCBkaXIpOwo+ID4gKwo+ID4gKyAgICAgICAvKiBOb3cgYWxsb2NhdGUgYW5kIHNldHVwIHRoZSBk ZXNjcmlwdG9yICovCj4gPiArICAgICAgIGQgPSBremFsbG9jKHNpemVvZigqZCksIEdGUF9BVE9N SUMpOwo+ID4gKyAgICAgICBpZiAoIWQpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIE5VTEw7 Cj4gPiArCj4gPiArICAgICAgIC8qIHNnbGVuIGlzIDEgKi8KPiA+ICsgICAgICAgZC0+YXZhaWxf bGVuID0gc2dfZG1hX2xlbihzZ2wpOwo+ID4gKyAgICAgICBjLT5yeF9zdGF0dXMgPSBkLT5hdmFp bF9sZW47Cj4gPiArCj4gPiArICAgICAgIHJldHVybiB2Y2hhbl90eF9wcmVwKCZjLT52YywgJmQt PnZkLCB0eF9mbGFncyk7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyB2b2lkIG10a191YXJ0X2Fw ZG1hX2lzc3VlX3BlbmRpbmcoc3RydWN0IGRtYV9jaGFuICpjaGFuKQo+ID4gK3sKPiA+ICsgICAg ICAgc3RydWN0IG10a19jaGFuICpjID0gdG9fbXRrX3VhcnRfYXBkbWFfY2hhbihjaGFuKTsKPiA+ ICsgICAgICAgc3RydWN0IHZpcnRfZG1hX2Rlc2MgKnZkOwo+ID4gKyAgICAgICB1bnNpZ25lZCBs b25nIGZsYWdzOwo+ID4gKwo+ID4gKyAgICAgICBzcGluX2xvY2tfaXJxc2F2ZSgmYy0+dmMubG9j aywgZmxhZ3MpOwo+ID4gKyAgICAgICBpZiAodmNoYW5faXNzdWVfcGVuZGluZygmYy0+dmMpKSB7 Cj4gPiArICAgICAgICAgICAgICAgdmQgPSB2Y2hhbl9uZXh0X2Rlc2MoJmMtPnZjKTsKPiA+ICsg ICAgICAgICAgICAgICBjLT5kZXNjID0gdG9fbXRrX3VhcnRfYXBkbWFfZGVzYygmdmQtPnR4KTsK PiA+ICsgICAgICAgfQo+ID4gKwo+ID4gKyAgICAgICBpZiAoYy0+ZGlyID09IERNQV9ERVZfVE9f TUVNKQo+ID4gKyAgICAgICAgICAgICAgIG10a191YXJ0X2FwZG1hX3N0YXJ0X3J4KGMpOwo+ID4g KyAgICAgICBlbHNlIGlmIChjLT5kaXIgPT0gRE1BX01FTV9UT19ERVYpCj4gPiArICAgICAgICAg ICAgICAgbXRrX3VhcnRfYXBkbWFfc3RhcnRfdHgoYyk7Cj4gPiArCj4gPiArICAgICAgIHNwaW5f dW5sb2NrX2lycXJlc3RvcmUoJmMtPnZjLmxvY2ssIGZsYWdzKTsKPiA+ICt9Cj4gPiArCj4gPiAr c3RhdGljIGludCBtdGtfdWFydF9hcGRtYV9zbGF2ZV9jb25maWcoc3RydWN0IGRtYV9jaGFuICpj aGFuLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgZG1hX3Ns YXZlX2NvbmZpZyAqY29uZmlnKQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IG10a19jaGFuICpj ID0gdG9fbXRrX3VhcnRfYXBkbWFfY2hhbihjaGFuKTsKPiA+ICsKPiA+ICsgICAgICAgbWVtY3B5 KCZjLT5jZmcsIGNvbmZpZywgc2l6ZW9mKCpjb25maWcpKTsKPiA+ICsKPiA+ICsgICAgICAgcmV0 dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgbXRrX3VhcnRfYXBkbWFfdGVybWlu YXRlX2FsbChzdHJ1Y3QgZG1hX2NoYW4gKmNoYW4pCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3Qg bXRrX2NoYW4gKmMgPSB0b19tdGtfdWFydF9hcGRtYV9jaGFuKGNoYW4pOwo+ID4gKyAgICAgICB1 bnNpZ25lZCBsb25nIGZsYWdzOwo+ID4gKyAgICAgICB1bnNpZ25lZCBpbnQgdG1wOwo+ID4gKyAg ICAgICBpbnQgcmV0Owo+ID4gKwo+ID4gKyAgICAgICBzcGluX2xvY2tfaXJxc2F2ZSgmYy0+dmMu bG9jaywgZmxhZ3MpOwo+ID4gKwo+ID4gKyAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBW RkZfRkxVU0gsIFZGRl9GTFVTSF9CKTsKPiA+ICsgICAgICAgLyogV2FpdCAxc2VjIGZvciBmbHVz aCwgY2FuJ3Qgc2xlZXAgKi8KPiA+ICsgICAgICAgcmV0ID0gcmVhZHhfcG9sbF90aW1lb3V0KHJl YWRsLCBjLT5iYXNlICsgVkZGX0ZMVVNILCB0bXAsCj4gPiArICAgICAgICAgICAgICAgICAgICAg ICB0bXAgIT0gVkZGX0ZMVVNIX0IsIDAsIDEwMDAwMDApOwo+IAo+IEl0IGlzIGV4dHJlbWVseSBi YWQgcGVuZGluZyBzbyBsb25nIGlzIGluIHRoZSBzcGluX2xvY2tfaXJxc2F2ZQoKSSB3aWxsIG1v ZGlmeSBpdCBpbiBuZXh0IHZlcnNpb24uCj4gCj4gPiArICAgICAgIGlmIChyZXQpCj4gPiArICAg ICAgICAgICAgICAgZGV2X2VycihjLT52Yy5jaGFuLmRldmljZS0+ZGV2LCAiZmx1c2g6IGZhaWws IGRlYnVnPTB4JXhcbiIsCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBtdGtfdWFydF9hcGRt YV9yZWFkKGMsIFZGRl9ERUJVR19TVEFUVVMpKTsKPiA+ICsKPiA+ICsgICAgICAgLyogc2V0IHN0 b3AgYXMgMSAtPiB3YWl0IHVudGlsIGVuIGlzIDAgLT4gc2V0IHN0b3AgYXMgMCAqLwo+ID4gKyAg ICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfU1RPUCwgVkZGX1NUT1BfQik7Cj4gPiAr ICAgICAgIHJldCA9IHJlYWR4X3BvbGxfdGltZW91dChyZWFkbCwgYy0+YmFzZSArIFZGRl9FTiwg dG1wLCAhdG1wLCAxMCwgMTAwKTsKPiA+ICsgICAgICAgaWYgKHJldCkKPiA+ICsgICAgICAgICAg ICAgICBkZXZfZXJyKGMtPnZjLmNoYW4uZGV2aWNlLT5kZXYsICJzdG9wOiBmYWlsLCBkZWJ1Zz0w eCV4XG4iLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgbXRrX3VhcnRfYXBkbWFfcmVhZChj LCBWRkZfREVCVUdfU1RBVFVTKSk7Cj4gPiArCj4gPiArICAgICAgIG10a191YXJ0X2FwZG1hX3dy aXRlKGMsIFZGRl9TVE9QLCBWRkZfU1RPUF9DTFJfQik7Cj4gPiArICAgICAgIG10a191YXJ0X2Fw ZG1hX3dyaXRlKGMsIFZGRl9JTlRfRU4sIFZGRl9JTlRfRU5fQ0xSX0IpOwo+ID4gKwo+ID4gKyAg ICAgICBpZiAoYy0+ZGlyID09IERNQV9ERVZfVE9fTUVNKQo+ID4gKyAgICAgICAgICAgICAgIG10 a191YXJ0X2FwZG1hX3dyaXRlKGMsIFZGRl9JTlRfRkxBRywgVkZGX1JYX0lOVF9DTFJfQik7Cj4g PiArICAgICAgIGVsc2UgaWYgKGMtPmRpciA9PSBETUFfTUVNX1RPX0RFVikKPiA+ICsgICAgICAg ICAgICAgICBtdGtfdWFydF9hcGRtYV93cml0ZShjLCBWRkZfSU5UX0ZMQUcsIFZGRl9UWF9JTlRf Q0xSX0IpOwo+ID4gKwo+ID4gKyAgICAgICBzcGluX3VubG9ja19pcnFyZXN0b3JlKCZjLT52Yy5s b2NrLCBmbGFncyk7Cj4gPiArCj4gPiArICAgICAgIHJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ ICtzdGF0aWMgaW50IG10a191YXJ0X2FwZG1hX2RldmljZV9wYXVzZShzdHJ1Y3QgZG1hX2NoYW4g KmNoYW4pCj4gPiArewo+ID4gKyAgICAgICAvKiBqdXN0IGZvciBjaGVjayBjYXBzIHBhc3MgKi8K PiA+ICsgICAgICAgZGV2X2VycihjaGFuLT5kZXZpY2UtPmRldiwgIlBhdXNlIGNhbid0IHN1cHBv cnRcbiIpOwo+ID4gKwo+IAo+IElmIHRoZSBkZXZpY2UgY2FuJ3Qgc3VwcG9ydCBoYXJkd2FyZSBw YXVzZSwgd2UgY2FuIGRvIGl0IGFzIGEgc29mdHdhcmUKPiBwYXVzZSBpbiBhbiBpbXBsZW1lbnRh dGlvbiBiYXNlZCBvbiB2ZGVzYy4KPiAKCm9rLCBpIHdpbGwgdHJ5IGl0LgoKPiA+ICsgICAgICAg cmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyB2b2lkIG10a191YXJ0X2FwZG1hX2Zy ZWUoc3RydWN0IG10a191YXJ0X2FwZG1hZGV2ICptdGtkKQo+ID4gK3sKPiA+ICsgICAgICAgd2hp bGUgKCFsaXN0X2VtcHR5KCZtdGtkLT5kZGV2LmNoYW5uZWxzKSkgewo+ID4gKyAgICAgICAgICAg ICAgIHN0cnVjdCBtdGtfY2hhbiAqYyA9IGxpc3RfZmlyc3RfZW50cnkoJm10a2QtPmRkZXYuY2hh bm5lbHMsCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBzdHJ1Y3QgbXRrX2NoYW4sIHZjLmNo YW4uZGV2aWNlX25vZGUpOwo+ID4gKwo+ID4gKyAgICAgICAgICAgICAgIGxpc3RfZGVsKCZjLT52 Yy5jaGFuLmRldmljZV9ub2RlKTsKPiA+ICsgICAgICAgICAgICAgICB0YXNrbGV0X2tpbGwoJmMt PnZjLnRhc2spOwo+ID4gKyAgICAgICB9Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBz dHJ1Y3Qgb2ZfZGV2aWNlX2lkIG10a191YXJ0X2FwZG1hX21hdGNoW10gPSB7Cj4gPiArICAgICAg IHsgLmNvbXBhdGlibGUgPSAibWVkaWF0ZWssbXQ2NTc3LXVhcnQtZG1hIiwgfSwKPiA+ICsgICAg ICAgeyAvKiBzZW50aW5lbCAqLyB9LAo+ID4gK307Cj4gPiArTU9EVUxFX0RFVklDRV9UQUJMRShv ZiwgbXRrX3VhcnRfYXBkbWFfbWF0Y2gpOwo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgbXRrX3VhcnRf YXBkbWFfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiA+ICt7Cj4gPiArICAg ICAgIHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAgPSBwZGV2LT5kZXYub2Zfbm9kZTsKPiA+ICsgICAg ICAgc3RydWN0IG10a191YXJ0X2FwZG1hZGV2ICptdGtkOwo+ID4gKyAgICAgICBzdHJ1Y3QgcmVz b3VyY2UgKnJlczsKPiA+ICsgICAgICAgc3RydWN0IG10a19jaGFuICpjOwo+ID4gKyAgICAgICBp bnQgYml0X21hc2sgPSAzMiwgcmM7Cj4gPiArICAgICAgIHVuc2lnbmVkIGludCBpOwo+ID4gKwo+ ID4gKyAgICAgICBtdGtkID0gZGV2bV9remFsbG9jKCZwZGV2LT5kZXYsIHNpemVvZigqbXRrZCks IEdGUF9LRVJORUwpOwo+ID4gKyAgICAgICBpZiAoIW10a2QpCj4gPiArICAgICAgICAgICAgICAg cmV0dXJuIC1FTk9NRU07Cj4gPiArCj4gPiArICAgICAgIG10a2QtPmNsayA9IGRldm1fY2xrX2dl dCgmcGRldi0+ZGV2LCBOVUxMKTsKPiA+ICsgICAgICAgaWYgKElTX0VSUihtdGtkLT5jbGspKSB7 Cj4gPiArICAgICAgICAgICAgICAgZGV2X2VycigmcGRldi0+ZGV2LCAiTm8gY2xvY2sgc3BlY2lm aWVkXG4iKTsKPiA+ICsgICAgICAgICAgICAgICByYyA9IFBUUl9FUlIobXRrZC0+Y2xrKTsKPiA+ ICsgICAgICAgICAgICAgICByZXR1cm4gcmM7Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAg ICAgaWYgKG9mX3Byb3BlcnR5X3JlYWRfYm9vbChucCwgIm1lZGlhdGVrLGRtYS0zM2JpdHMiKSkK PiA+ICsgICAgICAgICAgICAgICBtdGtkLT5zdXBwb3J0XzMzYml0cyA9IHRydWU7Cj4gPiArCj4g PiArICAgICAgIGlmIChtdGtkLT5zdXBwb3J0XzMzYml0cykKPiA+ICsgICAgICAgICAgICAgICBi aXRfbWFzayA9IDMzOwo+ID4gKwo+ID4gKyAgICAgICByYyA9IGRtYV9zZXRfbWFza19hbmRfY29o ZXJlbnQoJnBkZXYtPmRldiwgRE1BX0JJVF9NQVNLKGJpdF9tYXNrKSk7Cj4gPiArICAgICAgIGlm IChyYykKPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gcmM7Cj4gPiArCj4gPiArICAgICAgIGRt YV9jYXBfc2V0KERNQV9TTEFWRSwgbXRrZC0+ZGRldi5jYXBfbWFzayk7Cj4gPiArICAgICAgIG10 a2QtPmRkZXYuZGV2aWNlX2FsbG9jX2NoYW5fcmVzb3VyY2VzID0KPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgbXRrX3VhcnRfYXBkbWFfYWxsb2NfY2hhbl9yZXNvdXJjZXM7Cj4g PiArICAgICAgIG10a2QtPmRkZXYuZGV2aWNlX2ZyZWVfY2hhbl9yZXNvdXJjZXMgPQo+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBtdGtfdWFydF9hcGRtYV9mcmVlX2NoYW5fcmVz b3VyY2VzOwo+ID4gKyAgICAgICBtdGtkLT5kZGV2LmRldmljZV90eF9zdGF0dXMgPSBtdGtfdWFy dF9hcGRtYV90eF9zdGF0dXM7Cj4gPiArICAgICAgIG10a2QtPmRkZXYuZGV2aWNlX2lzc3VlX3Bl bmRpbmcgPSBtdGtfdWFydF9hcGRtYV9pc3N1ZV9wZW5kaW5nOwo+ID4gKyAgICAgICBtdGtkLT5k ZGV2LmRldmljZV9wcmVwX3NsYXZlX3NnID0gbXRrX3VhcnRfYXBkbWFfcHJlcF9zbGF2ZV9zZzsK PiA+ICsgICAgICAgbXRrZC0+ZGRldi5kZXZpY2VfY29uZmlnID0gbXRrX3VhcnRfYXBkbWFfc2xh dmVfY29uZmlnOwo+ID4gKyAgICAgICBtdGtkLT5kZGV2LmRldmljZV9wYXVzZSA9IG10a191YXJ0 X2FwZG1hX2RldmljZV9wYXVzZTsKPiA+ICsgICAgICAgbXRrZC0+ZGRldi5kZXZpY2VfdGVybWlu YXRlX2FsbCA9IG10a191YXJ0X2FwZG1hX3Rlcm1pbmF0ZV9hbGw7Cj4gPiArICAgICAgIG10a2Qt PmRkZXYuc3JjX2FkZHJfd2lkdGhzID0gQklUKERNQV9TTEFWRV9CVVNXSURUSF8xX0JZVEUpOwo+ ID4gKyAgICAgICBtdGtkLT5kZGV2LmRzdF9hZGRyX3dpZHRocyA9IEJJVChETUFfU0xBVkVfQlVT V0lEVEhfMV9CWVRFKTsKPiA+ICsgICAgICAgbXRrZC0+ZGRldi5kaXJlY3Rpb25zID0gQklUKERN QV9ERVZfVE9fTUVNKSB8IEJJVChETUFfTUVNX1RPX0RFVik7Cj4gPiArICAgICAgIG10a2QtPmRk ZXYucmVzaWR1ZV9ncmFudWxhcml0eSA9IERNQV9SRVNJRFVFX0dSQU5VTEFSSVRZX1NFR01FTlQ7 Cj4gPiArICAgICAgIG10a2QtPmRkZXYuZGV2ID0gJnBkZXYtPmRldjsKPiA+ICsgICAgICAgSU5J VF9MSVNUX0hFQUQoJm10a2QtPmRkZXYuY2hhbm5lbHMpOwo+ID4gKwo+ID4gKyAgICAgICBtdGtk LT5kbWFfcmVxdWVzdHMgPSBNVEtfVUFSVF9BUERNQV9OUl9WQ0hBTlM7Cj4gPiArICAgICAgIGlm IChvZl9wcm9wZXJ0eV9yZWFkX3UzMihucCwgImRtYS1yZXF1ZXN0cyIsICZtdGtkLT5kbWFfcmVx dWVzdHMpKSB7Cj4gPiArICAgICAgICAgICAgICAgZGV2X2luZm8oJnBkZXYtPmRldiwKPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgICAiVXNpbmcgJXUgYXMgbWlzc2luZyBkbWEtcmVxdWVzdHMg cHJvcGVydHlcbiIsCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgTVRLX1VBUlRfQVBETUFf TlJfVkNIQU5TKTsKPiA+ICsgICAgICAgfQo+ID4gKwo+ID4gKyAgICAgICBtdGtkLT5kbWFfaXJx ID0gZGV2bV9rY2FsbG9jKCZwZGV2LT5kZXYsIG10a2QtPmRtYV9yZXF1ZXN0cywKPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHNpemVvZigqbXRrZC0+ZG1hX2lycSksIEdGUF9L RVJORUwpOwo+ID4gKyAgICAgICBpZiAoIW10a2QtPmRtYV9pcnEpCj4gPiArICAgICAgICAgICAg ICAgcmV0dXJuIC1FTk9NRU07Cj4gPiArCj4gPiArICAgICAgIGZvciAoaSA9IDA7IGkgPCBtdGtk LT5kbWFfcmVxdWVzdHM7IGkrKykgewo+ID4gKyAgICAgICAgICAgICAgIGMgPSBkZXZtX2t6YWxs b2MobXRrZC0+ZGRldi5kZXYsIHNpemVvZigqYyksIEdGUF9LRVJORUwpOwo+ID4gKyAgICAgICAg ICAgICAgIGlmICghYykgewo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmMgPSAtRU5PREVW Owo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZ290byBlcnJfbm9fZG1hOwo+ID4gKyAgICAg ICAgICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAgICAgICAgICByZXMgPSBwbGF0Zm9ybV9nZXRf cmVzb3VyY2UocGRldiwgSU9SRVNPVVJDRV9NRU0sIGkpOwo+ID4gKyAgICAgICAgICAgICAgIGlm ICghcmVzKSB7Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICByYyA9IC1FTk9ERVY7Cj4gPiAr ICAgICAgICAgICAgICAgICAgICAgICBnb3RvIGVycl9ub19kbWE7Cj4gPiArICAgICAgICAgICAg ICAgfQo+ID4gKwo+ID4gKyAgICAgICAgICAgICAgIGMtPmJhc2UgPSBkZXZtX2lvcmVtYXBfcmVz b3VyY2UoJnBkZXYtPmRldiwgcmVzKTsKPiA+ICsgICAgICAgICAgICAgICBpZiAoSVNfRVJSKGMt PmJhc2UpKSB7Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICByYyA9IFBUUl9FUlIoYy0+YmFz ZSk7Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICBnb3RvIGVycl9ub19kbWE7Cj4gPiArICAg ICAgICAgICAgICAgfQo+ID4gKyAgICAgICAgICAgICAgIGMtPnJlcXVlc3RlZCA9IGZhbHNlOwo+ ID4gKyAgICAgICAgICAgICAgIGMtPnZjLmRlc2NfZnJlZSA9IG10a191YXJ0X2FwZG1hX2Rlc2Nf ZnJlZTsKPiA+ICsgICAgICAgICAgICAgICB2Y2hhbl9pbml0KCZjLT52YywgJm10a2QtPmRkZXYp Owo+ID4gKwo+ID4gKyAgICAgICAgICAgICAgIG10a2QtPmRtYV9pcnFbaV0gPSBwbGF0Zm9ybV9n ZXRfaXJxKHBkZXYsIGkpOwo+ID4gKyAgICAgICAgICAgICAgIGlmICgoaW50KW10a2QtPmRtYV9p cnFbaV0gPCAwKSB7Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICBkZXZfZXJyKCZwZGV2LT5k ZXYsICJmYWlsZWQgdG8gZ2V0IElSUVslZF1cbiIsIGkpOwo+ID4gKyAgICAgICAgICAgICAgICAg ICAgICAgcmMgPSAtRUlOVkFMOwo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZ290byBlcnJf bm9fZG1hOwo+ID4gKyAgICAgICAgICAgICAgIH0KPiA+ICsgICAgICAgfQo+ID4gKwo+ID4gKyAg ICAgICBwbV9ydW50aW1lX2VuYWJsZSgmcGRldi0+ZGV2KTsKPiA+ICsgICAgICAgcG1fcnVudGlt ZV9zZXRfYWN0aXZlKCZwZGV2LT5kZXYpOwo+ID4gKwo+ID4gKyAgICAgICByYyA9IGRtYV9hc3lu Y19kZXZpY2VfcmVnaXN0ZXIoJm10a2QtPmRkZXYpOwo+ID4gKyAgICAgICBpZiAocmMpCj4gPiAr ICAgICAgICAgICAgICAgZ290byBycG1fZGlzYWJsZTsKPiA+ICsKPiA+ICsgICAgICAgcGxhdGZv cm1fc2V0X2RydmRhdGEocGRldiwgbXRrZCk7Cj4gPiArCj4gPiArICAgICAgIC8qIERldmljZS10 cmVlIERNQSBjb250cm9sbGVyIHJlZ2lzdHJhdGlvbiAqLwo+ID4gKyAgICAgICByYyA9IG9mX2Rt YV9jb250cm9sbGVyX3JlZ2lzdGVyKG5wLCBvZl9kbWFfeGxhdGVfYnlfY2hhbl9pZCwgbXRrZCk7 Cj4gPiArICAgICAgIGlmIChyYykKPiA+ICsgICAgICAgICAgICAgICBnb3RvIGRtYV9yZW1vdmU7 Cj4gPiArCj4gPiArICAgICAgIHJldHVybiByYzsKPiA+ICsKPiA+ICtkbWFfcmVtb3ZlOgo+ID4g KyAgICAgICBkbWFfYXN5bmNfZGV2aWNlX3VucmVnaXN0ZXIoJm10a2QtPmRkZXYpOwo+ID4gK3Jw bV9kaXNhYmxlOgo+ID4gKyAgICAgICBwbV9ydW50aW1lX2Rpc2FibGUoJnBkZXYtPmRldik7Cj4g PiArZXJyX25vX2RtYToKPiA+ICsgICAgICAgbXRrX3VhcnRfYXBkbWFfZnJlZShtdGtkKTsKPiA+ ICsgICAgICAgcmV0dXJuIHJjOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IG10a191YXJ0 X2FwZG1hX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ID4gK3sKPiA+ICsg ICAgICAgc3RydWN0IG10a191YXJ0X2FwZG1hZGV2ICptdGtkID0gcGxhdGZvcm1fZ2V0X2RydmRh dGEocGRldik7Cj4gPiArCj4gPiArICAgICAgIGlmIChwZGV2LT5kZXYub2Zfbm9kZSkKPiA+ICsg ICAgICAgICAgICAgICBvZl9kbWFfY29udHJvbGxlcl9mcmVlKHBkZXYtPmRldi5vZl9ub2RlKTsK PiA+ICsKPiA+ICsgICAgICAgcG1fcnVudGltZV9kaXNhYmxlKCZwZGV2LT5kZXYpOwo+ID4gKyAg ICAgICBwbV9ydW50aW1lX3B1dF9ub2lkbGUoJnBkZXYtPmRldik7Cj4gCj4gVGhhdCBwbV9ydW50 aW1lX3B1dF9ub2lkbGUgc2hvdWxkIGJlIHJlbW92ZWQgb3IgaXQgY2F1c2VzIGFuCj4gaW5jb25z aXN0ZW5jeSB3aXRoIHRoZSBwcm9iZSBoYW5kbGVyLgo+IAoKT2ssIEkgd2lsbCByZW1vdmUgaXQu Cgo+ID4gKwo+ID4gKyAgICAgICBkbWFfYXN5bmNfZGV2aWNlX3VucmVnaXN0ZXIoJm10a2QtPmRk ZXYpOwo+ID4gKyAgICAgICBtdGtfdWFydF9hcGRtYV9mcmVlKG10a2QpOwo+ID4gKwo+ID4gKyAg ICAgICByZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArI2lmZGVmIENPTkZJR19QTV9TTEVFUAo+ ID4gK3N0YXRpYyBpbnQgbXRrX3VhcnRfYXBkbWFfc3VzcGVuZChzdHJ1Y3QgZGV2aWNlICpkZXYp Cj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgbXRrX3VhcnRfYXBkbWFkZXYgKm10a2QgPSBkZXZf Z2V0X2RydmRhdGEoZGV2KTsKPiA+ICsKPiA+ICsgICAgICAgaWYgKCFwbV9ydW50aW1lX3N1c3Bl bmRlZChkZXYpKQo+ID4gKyAgICAgICAgICAgICAgIGNsa19kaXNhYmxlX3VucHJlcGFyZShtdGtk LT5jbGspOwo+ID4gKwo+ID4gKyAgICAgICByZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArc3Rh dGljIGludCBtdGtfdWFydF9hcGRtYV9yZXN1bWUoc3RydWN0IGRldmljZSAqZGV2KQo+ID4gK3sK PiA+ICsgICAgICAgaW50IHJldDsKPiA+ICsgICAgICAgc3RydWN0IG10a191YXJ0X2FwZG1hZGV2 ICptdGtkID0gZGV2X2dldF9kcnZkYXRhKGRldik7Cj4gPiArCj4gPiArICAgICAgIGlmICghcG1f cnVudGltZV9zdXNwZW5kZWQoZGV2KSkgewo+ID4gKyAgICAgICAgICAgICAgIHJldCA9IGNsa19w cmVwYXJlX2VuYWJsZShtdGtkLT5jbGspOwo+ID4gKyAgICAgICAgICAgICAgIGlmIChyZXQpCj4g PiArICAgICAgICAgICAgICAgICAgICAgICByZXR1cm4gcmV0Owo+ID4gKyAgICAgICB9Cj4gPiAr Cj4gPiArICAgICAgIHJldHVybiAwOwo+ID4gK30KPiA+ICsjZW5kaWYgLyogQ09ORklHX1BNX1NM RUVQICovCj4gPiArCj4gPiArI2lmZGVmIENPTkZJR19QTQo+ID4gK3N0YXRpYyBpbnQgbXRrX3Vh cnRfYXBkbWFfcnVudGltZV9zdXNwZW5kKHN0cnVjdCBkZXZpY2UgKmRldikKPiA+ICt7Cj4gPiAr ICAgICAgIHN0cnVjdCBtdGtfdWFydF9hcGRtYWRldiAqbXRrZCA9IGRldl9nZXRfZHJ2ZGF0YShk ZXYpOwo+ID4gKwo+ID4gKyAgICAgICBjbGtfZGlzYWJsZV91bnByZXBhcmUobXRrZC0+Y2xrKTsK PiA+ICsKPiA+ICsgICAgICAgcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQg bXRrX3VhcnRfYXBkbWFfcnVudGltZV9yZXN1bWUoc3RydWN0IGRldmljZSAqZGV2KQo+ID4gK3sK PiA+ICsgICAgICAgaW50IHJldDsKPiA+ICsgICAgICAgc3RydWN0IG10a191YXJ0X2FwZG1hZGV2 ICptdGtkID0gZGV2X2dldF9kcnZkYXRhKGRldik7Cj4gPiArCj4gPiArICAgICAgIHJldCA9IGNs a19wcmVwYXJlX2VuYWJsZShtdGtkLT5jbGspOwo+ID4gKyAgICAgICBpZiAocmV0KQo+ID4gKyAg ICAgICAgICAgICAgIHJldHVybiByZXQ7Cj4gPiArCj4gPiArICAgICAgIHJldHVybiAwOwo+ID4g K30KPiA+ICsjZW5kaWYgLyogQ09ORklHX1BNICovCj4gPiArCj4gPiArc3RhdGljIGNvbnN0IHN0 cnVjdCBkZXZfcG1fb3BzIG10a191YXJ0X2FwZG1hX3BtX29wcyA9IHsKPiA+ICsgICAgICAgU0VU X1NZU1RFTV9TTEVFUF9QTV9PUFMobXRrX3VhcnRfYXBkbWFfc3VzcGVuZCwgbXRrX3VhcnRfYXBk bWFfcmVzdW1lKQo+ID4gKyAgICAgICBTRVRfUlVOVElNRV9QTV9PUFMobXRrX3VhcnRfYXBkbWFf cnVudGltZV9zdXNwZW5kLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgbXRrX3VhcnRf YXBkbWFfcnVudGltZV9yZXN1bWUsIE5VTEwpCj4gPiArfTsKPiAKPiBJdCBwcm9iYWJseSBjYXVz ZXMgYSBidWlsZCBlcnJvciB3aGVuIENPTkZJR19QTSBpcyBub3QgZW5hYmxlZC4KPiBhbmQgdXNl IGEgVU5JVkVSU0FMX0RFVl9QTV9PUFMgYmVjYXVzZSB0aGUgcnVudGltZSBzdXNwZW5kL3Jlc3Vt ZSBhbmQKPiBzeXN0ZW0gc3VzcGVuZC9yZXN1bWUgZm9yIHRoZSBkbWEgYXJlCj4gYWxtb3N0IHRo ZSBzYW1lLgo+IAoKSSByZW1lbWJlciB0aGF0IHRoZXNlIGhhZCB0ZXN0LiBJdCdzIGJ1aWxkIHBh c3MuCgo+ID4gKwo+ID4gK3N0YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIG10a191YXJ0X2Fw ZG1hX2RyaXZlciA9IHsKPiA+ICsgICAgICAgLnByb2JlICA9IG10a191YXJ0X2FwZG1hX3Byb2Jl LAo+ID4gKyAgICAgICAucmVtb3ZlID0gbXRrX3VhcnRfYXBkbWFfcmVtb3ZlLAo+ID4gKyAgICAg ICAuZHJpdmVyID0gewo+ID4gKyAgICAgICAgICAgICAgIC5uYW1lICAgICAgICAgICA9IEtCVUlM RF9NT0ROQU1FLAo+ID4gKyAgICAgICAgICAgICAgIC5wbSAgICAgICAgICAgICA9ICZtdGtfdWFy dF9hcGRtYV9wbV9vcHMsCj4gPiArICAgICAgICAgICAgICAgLm9mX21hdGNoX3RhYmxlID0gb2Zf bWF0Y2hfcHRyKG10a191YXJ0X2FwZG1hX21hdGNoKSwKPiA+ICsgICAgICAgfSwKPiA+ICt9Owo+ ID4gKwo+ID4gK21vZHVsZV9wbGF0Zm9ybV9kcml2ZXIobXRrX3VhcnRfYXBkbWFfZHJpdmVyKTsK PiA+ICsKPiA+ICtNT0RVTEVfREVTQ1JJUFRJT04oIk1lZGlhVGVrIFVBUlQgQVBETUEgQ29udHJv bGxlciBEcml2ZXIiKTsKPiA+ICtNT0RVTEVfQVVUSE9SKCJMb25nIENoZW5nIDxsb25nLmNoZW5n QG1lZGlhdGVrLmNvbT4iKTsKPiA+ICtNT0RVTEVfTElDRU5TRSgiR1BMIHYyIik7Cj4gPiArCj4g PiAtLQo+ID4gMS43LjkuNQo+ID4K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E555C10F14 for ; Thu, 11 Apr 2019 08:20:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2A4722082E for ; Thu, 11 Apr 2019 08:20:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726145AbfDKIUW (ORCPT ); Thu, 11 Apr 2019 04:20:22 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:2138 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726137AbfDKIUW (ORCPT ); Thu, 11 Apr 2019 04:20:22 -0400 X-UUID: 25e03eb0d8d94b4aaab3b0fa8c41104b-20190411 X-UUID: 25e03eb0d8d94b4aaab3b0fa8c41104b-20190411 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 436491658; Thu, 11 Apr 2019 16:20:11 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 11 Apr 2019 16:20:10 +0800 Received: from [10.17.3.153] (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 11 Apr 2019 16:20:06 +0800 Message-ID: <1554970806.14150.16.camel@mhfsdcap03> Subject: Re: [PATCH v11 1/4] dmaengine: 8250_mtk_dma: add MediaTek uart DMA support From: Long Cheng To: Sean Wang CC: Vinod Koul , Randy Dunlap , "Rob Herring" , Mark Rutland , "Ryder Lee" , Nicolas Boichat , Matthias Brugger , Dan Williams , Greg Kroah-Hartman , Jiri Slaby , Sean Wang , , , , , , , srv_heupstream , Yingjoe Chen , YT Shen , Zhenbao Liu Date: Thu, 11 Apr 2019 16:20:06 +0800 In-Reply-To: References: <1551923135-32479-1-git-send-email-long.cheng@mediatek.com> <1551923135-32479-2-git-send-email-long.cheng@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190411082006.cJgblHtw0CoTOIxfEYZW1SFPiRVivSrFz2pfkNJX36w@z> On Sun, 2019-03-10 at 17:31 -0700, Sean Wang wrote: > Hi, Long > > List some comments as the below and this week I will find a board to > test and then improve the driver. > > Sean > > On Wed, Mar 6, 2019 at 5:45 PM Long Cheng wrote: > > > > In DMA engine framework, add 8250 uart dma to support MediaTek uart. > > If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve > > the performance, can enable the function. > > > > Signed-off-by: Long Cheng > > --- > > drivers/dma/mediatek/Kconfig | 11 + > > drivers/dma/mediatek/Makefile | 1 + > > drivers/dma/mediatek/mtk-uart-apdma.c | 660 +++++++++++++++++++++++++++++++++ > > 3 files changed, 672 insertions(+) > > create mode 100644 drivers/dma/mediatek/mtk-uart-apdma.c > > > > diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig > > index 680fc05..ac49eb6 100644 > > --- a/drivers/dma/mediatek/Kconfig > > +++ b/drivers/dma/mediatek/Kconfig > > @@ -24,3 +24,14 @@ config MTK_CQDMA > > > > This controller provides the channels which is dedicated to > > memory-to-memory transfer to offload from CPU. > > + > > +config MTK_UART_APDMA > > + tristate "MediaTek SoCs APDMA support for UART" > > + depends on OF && SERIAL_8250_MT6577 > > + select DMA_ENGINE > > + select DMA_VIRTUAL_CHANNELS > > + help > > + Support for the UART DMA engine found on MediaTek MTK SoCs. > > + When SERIAL_8250_MT6577 is enabled, and if you want to use DMA, > > + you can enable the config. The DMA engine can only be used > > + with MediaTek SoCs. > > diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile > > index 41bb381..61a6d29 100644 > > --- a/drivers/dma/mediatek/Makefile > > +++ b/drivers/dma/mediatek/Makefile > > @@ -1,2 +1,3 @@ > > +obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o > > obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o > > obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o > > diff --git a/drivers/dma/mediatek/mtk-uart-apdma.c b/drivers/dma/mediatek/mtk-uart-apdma.c > > new file mode 100644 > > index 0000000..9ed7a49 > > --- /dev/null > > +++ b/drivers/dma/mediatek/mtk-uart-apdma.c > > @@ -0,0 +1,660 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * MediaTek Uart APDMA driver. > > + * > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Long Cheng > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "../virt-dma.h" > > + > > +/* The default number of virtual channel */ > > +#define MTK_UART_APDMA_NR_VCHANS 8 > > + > > +#define VFF_EN_B BIT(0) > > +#define VFF_STOP_B BIT(0) > > +#define VFF_FLUSH_B BIT(0) > > +#define VFF_4G_SUPPORT_B BIT(0) > > +#define VFF_RX_INT_EN0_B BIT(0) /* rx valid size >= vff thre */ > > +#define VFF_RX_INT_EN1_B BIT(1) > > +#define VFF_TX_INT_EN_B BIT(0) /* tx left size >= vff thre */ > > +#define VFF_WARM_RST_B BIT(0) > > +#define VFF_RX_INT_CLR_B (BIT(0) | BIT(1)) > > +#define VFF_TX_INT_CLR_B 0 > > +#define VFF_STOP_CLR_B 0 > > +#define VFF_INT_EN_CLR_B 0 > > +#define VFF_4G_SUPPORT_CLR_B 0 > > + > > +/* interrupt trigger level for tx */ > > +#define VFF_TX_THRE(n) ((n) * 7 / 8) > > +/* interrupt trigger level for rx */ > > +#define VFF_RX_THRE(n) ((n) * 3 / 4) > > + > > +#define VFF_RING_SIZE 0xffffU > > +/* invert this bit when wrap ring head again */ > > +#define VFF_RING_WRAP 0x10000U > > + > > +#define VFF_INT_FLAG 0x00 > > +#define VFF_INT_EN 0x04 > > +#define VFF_EN 0x08 > > +#define VFF_RST 0x0c > > +#define VFF_STOP 0x10 > > +#define VFF_FLUSH 0x14 > > +#define VFF_ADDR 0x1c > > +#define VFF_LEN 0x24 > > +#define VFF_THRE 0x28 > > +#define VFF_WPT 0x2c > > +#define VFF_RPT 0x30 > > +/* TX: the buffer size HW can read. RX: the buffer size SW can read. */ > > +#define VFF_VALID_SIZE 0x3c > > +/* TX: the buffer size SW can write. RX: the buffer size HW can write. */ > > +#define VFF_LEFT_SIZE 0x40 > > +#define VFF_DEBUG_STATUS 0x50 > > +#define VFF_4G_SUPPORT 0x54 > > + > > +struct mtk_uart_apdmadev { > > + struct dma_device ddev; > > + struct clk *clk; > > + bool support_33bits; > > + unsigned int dma_requests; > > + unsigned int *dma_irq; > > +}; > > + > > +struct mtk_uart_apdma_desc { > > + struct virt_dma_desc vd; > > + > > + unsigned int avail_len; > > +}; > > + > > +struct mtk_chan { > > + struct virt_dma_chan vc; > > + struct dma_slave_config cfg; > > + void __iomem *base; > > + struct mtk_uart_apdma_desc *desc; > > + > > + enum dma_transfer_direction dir; > > + > > + bool requested; > > + > > + unsigned int rx_status; > > +}; > > + > > +static inline struct mtk_uart_apdmadev * > > +to_mtk_uart_apdma_dev(struct dma_device *d) > > +{ > > + return container_of(d, struct mtk_uart_apdmadev, ddev); > > +} > > + > > +static inline struct mtk_chan *to_mtk_uart_apdma_chan(struct dma_chan *c) > > +{ > > + return container_of(c, struct mtk_chan, vc.chan); > > +} > > + > > +static inline struct mtk_uart_apdma_desc *to_mtk_uart_apdma_desc > > + (struct dma_async_tx_descriptor *t) > > +{ > > + return container_of(t, struct mtk_uart_apdma_desc, vd.tx); > > +} > > + > > +static void mtk_uart_apdma_write(struct mtk_chan *c, > > + unsigned int reg, unsigned int val) > > +{ > > + writel(val, c->base + reg); > > +} > > + > > +static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg) > > +{ > > + return readl(c->base + reg); > > +} > > + > > +static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd) > > +{ > > + struct dma_chan *chan = vd->tx.chan; > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + > > + kfree(c->desc); > > +} > > + > > +static void mtk_uart_apdma_start_tx(struct mtk_chan *c) > > +{ > > + unsigned int len, send, left, wpt, d_wpt, tmp; > > + int ret; > > + > > + left = mtk_uart_apdma_read(c, VFF_LEFT_SIZE); > > + if (!left) { > > + mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B); > > + return; > > + } > > + > > + /* Wait 1sec for flush, can't sleep */ > > + ret = readx_poll_timeout(readl, c->base + VFF_FLUSH, tmp, > > + tmp != VFF_FLUSH_B, 0, 1000000); > > It is really not a good idea that polling up to 1 second in an > interrupt context. > I will modify it in next version. > > + if (ret) > > + dev_warn(c->vc.chan.device->dev, "tx: fail, debug=0x%x\n", > > + mtk_uart_apdma_read(c, VFF_DEBUG_STATUS)); > > + > > + send = min_t(unsigned int, left, c->desc->avail_len); > > + wpt = mtk_uart_apdma_read(c, VFF_WPT); > > + len = c->cfg.dst_port_window_size; > > + > > + d_wpt = wpt + send; > > + if ((d_wpt & VFF_RING_SIZE) >= len) { > > I am confused what size of VFF is. Either VFF_RING_SIZE or > c->cfg.dst_port_window_size? > VFF_RRING_SIZE is max length that HW can support.The c->cfg.dst_port_window_size is actual length. > > + d_wpt = d_wpt - len; > > + d_wpt = d_wpt ^ VFF_RING_WRAP; > > + } > > + mtk_uart_apdma_write(c, VFF_WPT, d_wpt); > > + > > + c->desc->avail_len -= send; > > + > > + mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B); > > Why should we need to program interrupt enabled bit again? HW request. the step is must. > > > + if (mtk_uart_apdma_read(c, VFF_FLUSH) == 0U) > > + mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B); > > +} > > + > > +static void mtk_uart_apdma_start_rx(struct mtk_chan *c) > > +{ > > + struct mtk_uart_apdma_desc *d = c->desc; > > + unsigned int len, wg, rg; > > + int cnt; > > + > > + if ((mtk_uart_apdma_read(c, VFF_VALID_SIZE) == 0U) || > > + !d || !vchan_next_desc(&c->vc)) > > + return; > > If the current descriptor is not available, the hardware should be > idle or stopped. so I think the condition can be removed or there is > somewhere your handle descriptors incorrectly. I will modify it in next version. > > > + > > + len = c->cfg.src_port_window_size; > > + rg = mtk_uart_apdma_read(c, VFF_RPT); > > + wg = mtk_uart_apdma_read(c, VFF_WPT); > > + cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE); > > Is it possible that rg and wg would be greater than VFF_RING_SIZE? > No. > > + /* > > + * The buffer is ring buffer. If wrap bit different, > > + * represents the start of the next cycle for WPT > > + */ > > + if ((rg ^ wg) & VFF_RING_WRAP) > > + cnt += len; > > Again, I am confused what size of VFF is. Either VFF_RING_SIZE or > c->cfg.dst_port_window_size? > > > + > > + c->rx_status = d->avail_len - cnt; > > + mtk_uart_apdma_write(c, VFF_RPT, wg); > > + > > + list_del(&d->vd.node); > > + vchan_cookie_complete(&d->vd); > > +} > > + > > +static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id) > > +{ > > + struct dma_chan *chan = (struct dma_chan *)dev_id; > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + struct mtk_uart_apdma_desc *d; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&c->vc.lock, flags); > > + if (c->dir == DMA_DEV_TO_MEM) { > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); > > + mtk_uart_apdma_start_rx(c); > > + } else if (c->dir == DMA_MEM_TO_DEV) { > > + d = c->desc; > > + > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); > > + > > + if (d->avail_len != 0U) { > > + mtk_uart_apdma_start_tx(c); > > + } else { > > + list_del(&d->vd.node); > > + vchan_cookie_complete(&d->vd); > > + } > > + } > > + spin_unlock_irqrestore(&c->vc.lock, flags); > > + > > + return IRQ_HANDLED; > > +} > > + > > +static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan) > > +{ > > + struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device); > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + unsigned int tmp; > > + int ret; > > + > > + pm_runtime_get_sync(mtkd->ddev.dev); > > Add an error handling, something like > > err = pm_runtime_get_sync(mtkd->ddev.dev); > if (err < 0) { > pm_runtime_put_noidle(dev); > ... > } > I will modify it in next version. > > + > > + mtk_uart_apdma_write(c, VFF_ADDR, 0); > > + mtk_uart_apdma_write(c, VFF_THRE, 0); > > + mtk_uart_apdma_write(c, VFF_LEN, 0); > > + mtk_uart_apdma_write(c, VFF_RST, VFF_WARM_RST_B); > > + > > + ret = readx_poll_timeout(readl, c->base + VFF_EN, tmp, !tmp, 10, 100); > > + if (ret) { > > + dev_err(chan->device->dev, "dma reset: fail, timeout\n"); > > + return ret; > > + } > > + > > + if (!c->requested) { > > + c->requested = true; > > The variable c->requested can be saved since the same channel > shouldn't be requested more one time > I will modify it in next version. > > + ret = request_irq(mtkd->dma_irq[chan->chan_id], > > + mtk_uart_apdma_irq_handler, IRQF_TRIGGER_NONE, > > + KBUILD_MODNAME, chan); > > + if (ret < 0) { > > + dev_err(chan->device->dev, "Can't request dma IRQ\n"); > > + return -EINVAL; > > + } > > + } > > + > > + if (mtkd->support_33bits) > > + mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B); > > + > > + return ret; > > +} > > + > > +static void mtk_uart_apdma_free_chan_resources(struct dma_chan *chan) > > +{ > > + struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device); > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + > > + if (c->requested) { > > ditto as the above I will modify it in next version. > > > + c->requested = false; > > + free_irq(mtkd->dma_irq[chan->chan_id], chan); > > + } > > + > > + tasklet_kill(&c->vc.task); > > + > > + vchan_free_chan_resources(&c->vc); > > + > > + pm_runtime_put_sync(mtkd->ddev.dev); > > +} > > + > > +static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan, > > + dma_cookie_t cookie, > > + struct dma_tx_state *txstate) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + enum dma_status ret; > > + > > + ret = dma_cookie_status(chan, cookie, txstate); > > + > > + dma_set_residue(txstate, c->rx_status); > > + > > The handling is not enough. You should get the descriptor > corresponding to the cookie and then calculate and return the > ->tx_status by the descriptor > Because UART can't get any interrupt except DMA interrupt. So in APDMA, need notify UART to get data. And then descriptor will be released. So Need keep the solution. > > + return ret; > > +} > > + > > +static void mtk_uart_apdma_config_write(struct dma_chan *chan, > > + struct dma_slave_config *cfg, > > + enum dma_transfer_direction dir) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + struct mtk_uart_apdmadev *mtkd = > > + to_mtk_uart_apdma_dev(c->vc.chan.device); > > + unsigned int tmp; > > + > > + if (mtk_uart_apdma_read(c, VFF_EN) == VFF_EN_B) > > + return; > > + > > + c->dir = dir; > > The direction is fixed by the device, I don't think it is required to > keep it in a software state. Need save it. Because RX and TX isn't all same. > > > + > > + if (dir == DMA_DEV_TO_MEM) { > > + tmp = cfg->src_port_window_size; > > + > > + mtk_uart_apdma_write(c, VFF_ADDR, cfg->src_addr); > > That is wrong. ->src_addr is the physical address where DMA slave data > should be read (RX), not the memory address. > > You should program the register VFF_ADDR and VFF_LEN by sg address and > length from device_prep_slave_sg. I will modify it in next version. > > > + mtk_uart_apdma_write(c, VFF_LEN, tmp); > > + mtk_uart_apdma_write(c, VFF_THRE, VFF_RX_THRE(tmp)); > > + mtk_uart_apdma_write(c, VFF_INT_EN, > > + VFF_RX_INT_EN0_B | VFF_RX_INT_EN1_B); > > + mtk_uart_apdma_write(c, VFF_RPT, 0); > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); > > + } else if (dir == DMA_MEM_TO_DEV) { > > + tmp = cfg->dst_port_window_size; > > + > > + mtk_uart_apdma_write(c, VFF_ADDR, cfg->dst_addr); > > That is also wrong. st_addr: this is the physical address where DMA > slave data should be written (TX), not the memory address similar to > the above explanation. I will modify it in next version. > > > + mtk_uart_apdma_write(c, VFF_LEN, tmp); > > + mtk_uart_apdma_write(c, VFF_THRE, VFF_TX_THRE(tmp)); > > + mtk_uart_apdma_write(c, VFF_WPT, 0); > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); > > + } > > + > > + mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B); > > + > > + if (mtkd->support_33bits) > > + mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_B); > > + > > + if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B) > > + dev_err(chan->device->dev, "dir[%d] fail\n", dir); > > +} > > + > > +/* > > + * dmaengine_prep_slave_single will call the function. and sglen is 1. > > + * 8250 uart using one ring buffer, and deal with one sg. > > + */ > > +static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg > > + (struct dma_chan *chan, struct scatterlist *sgl, > > + unsigned int sglen, enum dma_transfer_direction dir, > > + unsigned long tx_flags, void *context) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + struct mtk_uart_apdma_desc *d; > > + > > + if (!is_slave_direction(dir)) > > + return NULL; > > + > > + mtk_uart_apdma_config_write(chan, &c->cfg, dir); > > + > > + /* Now allocate and setup the descriptor */ > > + d = kzalloc(sizeof(*d), GFP_ATOMIC); > > + if (!d) > > + return NULL; > > + > > + /* sglen is 1 */ > > + d->avail_len = sg_dma_len(sgl); > > + c->rx_status = d->avail_len; > > + > > + return vchan_tx_prep(&c->vc, &d->vd, tx_flags); > > +} > > + > > +static void mtk_uart_apdma_issue_pending(struct dma_chan *chan) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + struct virt_dma_desc *vd; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&c->vc.lock, flags); > > + if (vchan_issue_pending(&c->vc)) { > > + vd = vchan_next_desc(&c->vc); > > + c->desc = to_mtk_uart_apdma_desc(&vd->tx); > > + } > > + > > + if (c->dir == DMA_DEV_TO_MEM) > > + mtk_uart_apdma_start_rx(c); > > + else if (c->dir == DMA_MEM_TO_DEV) > > + mtk_uart_apdma_start_tx(c); > > + > > + spin_unlock_irqrestore(&c->vc.lock, flags); > > +} > > + > > +static int mtk_uart_apdma_slave_config(struct dma_chan *chan, > > + struct dma_slave_config *config) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + > > + memcpy(&c->cfg, config, sizeof(*config)); > > + > > + return 0; > > +} > > + > > +static int mtk_uart_apdma_terminate_all(struct dma_chan *chan) > > +{ > > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan); > > + unsigned long flags; > > + unsigned int tmp; > > + int ret; > > + > > + spin_lock_irqsave(&c->vc.lock, flags); > > + > > + mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B); > > + /* Wait 1sec for flush, can't sleep */ > > + ret = readx_poll_timeout(readl, c->base + VFF_FLUSH, tmp, > > + tmp != VFF_FLUSH_B, 0, 1000000); > > It is extremely bad pending so long is in the spin_lock_irqsave I will modify it in next version. > > > + if (ret) > > + dev_err(c->vc.chan.device->dev, "flush: fail, debug=0x%x\n", > > + mtk_uart_apdma_read(c, VFF_DEBUG_STATUS)); > > + > > + /* set stop as 1 -> wait until en is 0 -> set stop as 0 */ > > + mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_B); > > + ret = readx_poll_timeout(readl, c->base + VFF_EN, tmp, !tmp, 10, 100); > > + if (ret) > > + dev_err(c->vc.chan.device->dev, "stop: fail, debug=0x%x\n", > > + mtk_uart_apdma_read(c, VFF_DEBUG_STATUS)); > > + > > + mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_CLR_B); > > + mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B); > > + > > + if (c->dir == DMA_DEV_TO_MEM) > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B); > > + else if (c->dir == DMA_MEM_TO_DEV) > > + mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B); > > + > > + spin_unlock_irqrestore(&c->vc.lock, flags); > > + > > + return 0; > > +} > > + > > +static int mtk_uart_apdma_device_pause(struct dma_chan *chan) > > +{ > > + /* just for check caps pass */ > > + dev_err(chan->device->dev, "Pause can't support\n"); > > + > > If the device can't support hardware pause, we can do it as a software > pause in an implementation based on vdesc. > ok, i will try it. > > + return 0; > > +} > > + > > +static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd) > > +{ > > + while (!list_empty(&mtkd->ddev.channels)) { > > + struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels, > > + struct mtk_chan, vc.chan.device_node); > > + > > + list_del(&c->vc.chan.device_node); > > + tasklet_kill(&c->vc.task); > > + } > > +} > > + > > +static const struct of_device_id mtk_uart_apdma_match[] = { > > + { .compatible = "mediatek,mt6577-uart-dma", }, > > + { /* sentinel */ }, > > +}; > > +MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match); > > + > > +static int mtk_uart_apdma_probe(struct platform_device *pdev) > > +{ > > + struct device_node *np = pdev->dev.of_node; > > + struct mtk_uart_apdmadev *mtkd; > > + struct resource *res; > > + struct mtk_chan *c; > > + int bit_mask = 32, rc; > > + unsigned int i; > > + > > + mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL); > > + if (!mtkd) > > + return -ENOMEM; > > + > > + mtkd->clk = devm_clk_get(&pdev->dev, NULL); > > + if (IS_ERR(mtkd->clk)) { > > + dev_err(&pdev->dev, "No clock specified\n"); > > + rc = PTR_ERR(mtkd->clk); > > + return rc; > > + } > > + > > + if (of_property_read_bool(np, "mediatek,dma-33bits")) > > + mtkd->support_33bits = true; > > + > > + if (mtkd->support_33bits) > > + bit_mask = 33; > > + > > + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask)); > > + if (rc) > > + return rc; > > + > > + dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask); > > + mtkd->ddev.device_alloc_chan_resources = > > + mtk_uart_apdma_alloc_chan_resources; > > + mtkd->ddev.device_free_chan_resources = > > + mtk_uart_apdma_free_chan_resources; > > + mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status; > > + mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending; > > + mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg; > > + mtkd->ddev.device_config = mtk_uart_apdma_slave_config; > > + mtkd->ddev.device_pause = mtk_uart_apdma_device_pause; > > + mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all; > > + mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); > > + mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE); > > + mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); > > + mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; > > + mtkd->ddev.dev = &pdev->dev; > > + INIT_LIST_HEAD(&mtkd->ddev.channels); > > + > > + mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS; > > + if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) { > > + dev_info(&pdev->dev, > > + "Using %u as missing dma-requests property\n", > > + MTK_UART_APDMA_NR_VCHANS); > > + } > > + > > + mtkd->dma_irq = devm_kcalloc(&pdev->dev, mtkd->dma_requests, > > + sizeof(*mtkd->dma_irq), GFP_KERNEL); > > + if (!mtkd->dma_irq) > > + return -ENOMEM; > > + > > + for (i = 0; i < mtkd->dma_requests; i++) { > > + c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL); > > + if (!c) { > > + rc = -ENODEV; > > + goto err_no_dma; > > + } > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, i); > > + if (!res) { > > + rc = -ENODEV; > > + goto err_no_dma; > > + } > > + > > + c->base = devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(c->base)) { > > + rc = PTR_ERR(c->base); > > + goto err_no_dma; > > + } > > + c->requested = false; > > + c->vc.desc_free = mtk_uart_apdma_desc_free; > > + vchan_init(&c->vc, &mtkd->ddev); > > + > > + mtkd->dma_irq[i] = platform_get_irq(pdev, i); > > + if ((int)mtkd->dma_irq[i] < 0) { > > + dev_err(&pdev->dev, "failed to get IRQ[%d]\n", i); > > + rc = -EINVAL; > > + goto err_no_dma; > > + } > > + } > > + > > + pm_runtime_enable(&pdev->dev); > > + pm_runtime_set_active(&pdev->dev); > > + > > + rc = dma_async_device_register(&mtkd->ddev); > > + if (rc) > > + goto rpm_disable; > > + > > + platform_set_drvdata(pdev, mtkd); > > + > > + /* Device-tree DMA controller registration */ > > + rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd); > > + if (rc) > > + goto dma_remove; > > + > > + return rc; > > + > > +dma_remove: > > + dma_async_device_unregister(&mtkd->ddev); > > +rpm_disable: > > + pm_runtime_disable(&pdev->dev); > > +err_no_dma: > > + mtk_uart_apdma_free(mtkd); > > + return rc; > > +} > > + > > +static int mtk_uart_apdma_remove(struct platform_device *pdev) > > +{ > > + struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev); > > + > > + if (pdev->dev.of_node) > > + of_dma_controller_free(pdev->dev.of_node); > > + > > + pm_runtime_disable(&pdev->dev); > > + pm_runtime_put_noidle(&pdev->dev); > > That pm_runtime_put_noidle should be removed or it causes an > inconsistency with the probe handler. > Ok, I will remove it. > > + > > + dma_async_device_unregister(&mtkd->ddev); > > + mtk_uart_apdma_free(mtkd); > > + > > + return 0; > > +} > > + > > +#ifdef CONFIG_PM_SLEEP > > +static int mtk_uart_apdma_suspend(struct device *dev) > > +{ > > + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); > > + > > + if (!pm_runtime_suspended(dev)) > > + clk_disable_unprepare(mtkd->clk); > > + > > + return 0; > > +} > > + > > +static int mtk_uart_apdma_resume(struct device *dev) > > +{ > > + int ret; > > + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); > > + > > + if (!pm_runtime_suspended(dev)) { > > + ret = clk_prepare_enable(mtkd->clk); > > + if (ret) > > + return ret; > > + } > > + > > + return 0; > > +} > > +#endif /* CONFIG_PM_SLEEP */ > > + > > +#ifdef CONFIG_PM > > +static int mtk_uart_apdma_runtime_suspend(struct device *dev) > > +{ > > + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); > > + > > + clk_disable_unprepare(mtkd->clk); > > + > > + return 0; > > +} > > + > > +static int mtk_uart_apdma_runtime_resume(struct device *dev) > > +{ > > + int ret; > > + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev); > > + > > + ret = clk_prepare_enable(mtkd->clk); > > + if (ret) > > + return ret; > > + > > + return 0; > > +} > > +#endif /* CONFIG_PM */ > > + > > +static const struct dev_pm_ops mtk_uart_apdma_pm_ops = { > > + SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume) > > + SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend, > > + mtk_uart_apdma_runtime_resume, NULL) > > +}; > > It probably causes a build error when CONFIG_PM is not enabled. > and use a UNIVERSAL_DEV_PM_OPS because the runtime suspend/resume and > system suspend/resume for the dma are > almost the same. > I remember that these had test. It's build pass. > > + > > +static struct platform_driver mtk_uart_apdma_driver = { > > + .probe = mtk_uart_apdma_probe, > > + .remove = mtk_uart_apdma_remove, > > + .driver = { > > + .name = KBUILD_MODNAME, > > + .pm = &mtk_uart_apdma_pm_ops, > > + .of_match_table = of_match_ptr(mtk_uart_apdma_match), > > + }, > > +}; > > + > > +module_platform_driver(mtk_uart_apdma_driver); > > + > > +MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver"); > > +MODULE_AUTHOR("Long Cheng "); > > +MODULE_LICENSE("GPL v2"); > > + > > -- > > 1.7.9.5 > >