From: Jon Hunter <jonathanh@nvidia.com>
To: Laxman Dewangan <ldewangan@nvidia.com>, Vinod Koul <vkoul@kernel.org>
Cc: <dmaengine@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Sameer Pujar <spujar@nvidia.com>,
Jon Hunter <jonathanh@nvidia.com>
Subject: [PATCH 3/3] dmaengine: tegra210-adma: Fix spelling
Date: Thu, 16 May 2019 16:53:54 +0100 [thread overview]
Message-ID: <1558022034-19911-4-git-send-email-jonathanh@nvidia.com> (raw)
In-Reply-To: <1558022034-19911-1-git-send-email-jonathanh@nvidia.com>
Correct spelling of 'register' in Tegra210 ADMA driver.
Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/dma/tegra210-adma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index 3f50fd11c380..17ea4dd99c62 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -95,7 +95,7 @@ struct tegra_adma;
* @global_int_clear: Register offset of DMA global interrupt clear.
* @ch_req_tx_shift: Register offset for AHUB transmit channel select.
* @ch_req_rx_shift: Register offset for AHUB receive channel select.
- * @ch_base_offset: Reister offset of DMA channel registers.
+ * @ch_base_offset: Register offset of DMA channel registers.
* @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
* @ch_req_mask: Mask for Tx or Rx channel select.
* @ch_req_max: Maximum number of Tx or Rx channels available.
--
2.7.4
next prev parent reply other threads:[~2019-05-16 15:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 15:53 [PATCH 0/3] dmaengine: tegra210-adma: Fixes for v5.2 Jon Hunter
2019-05-16 15:53 ` [PATCH 1/3] dmaengine: tegra210-adma: Fix crash during probe Jon Hunter
2019-05-16 15:53 ` [PATCH 2/3] dmaengine: tegra210-adma: Fix channel FIFO configuration Jon Hunter
2019-05-16 15:53 ` Jon Hunter [this message]
2019-05-21 5:11 ` [PATCH 0/3] dmaengine: tegra210-adma: Fixes for v5.2 Vinod Koul
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