Re: [Patch v1 2/4] dma: tegra: Adding Tegra GPC DMA controller driver

kernel test robot
2020-07-20T12:47:48Z

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Hi Rajesh,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on arm64/for-next/core tegra/for-next linus/master v5.8-rc6 next-20200717]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Rajesh-Gumasta/Add-Nvidia-Tegra-GPC-DMA-driver/20200720-143607
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
reproduce (this is a W=1 build):
# save the attached .config to linux build tree
make W=1 ARCH=i386

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra-gpc-dma.c:870:41: warning: right shift count >= width of type [-Wshift-count-overflow]
870 | sg_req->ch_regs.high_addr_ptr = ((dest >> 32) &
| ^~
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra-gpc-dma.c:964:39: warning: right shift count >= width of type [-Wshift-count-overflow]
964 | sg_req->ch_regs.high_addr_ptr = (src >> 32) &
| ^~
drivers/dma/tegra-gpc-dma.c:966:42: warning: right shift count >= width of type [-Wshift-count-overflow]
966 | sg_req->ch_regs.high_addr_ptr |= ((dest >> 32) &
| ^~
drivers/dma/tegra-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra-gpc-dma.c:1095:41: warning: right shift count >= width of type [-Wshift-count-overflow]
1095 | sg_req->ch_regs.high_addr_ptr = (mem >> 32) &
| ^~
drivers/dma/tegra-gpc-dma.c:1100:42: warning: right shift count >= width of type [-Wshift-count-overflow]
1100 | sg_req->ch_regs.high_addr_ptr = ((mem >> 32) &
| ^~

vim +870 drivers/dma/tegra-gpc-dma.c

804
805 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_memset(
806 struct dma_chan *dc, dma_addr_t dest, int value, size_t len,
807 unsigned long flags)
808 {
809 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
810 struct tegra_dma_desc *dma_desc;
811 struct list_head req_list;
812 struct tegra_dma_sg_req *sg_req = NULL;
813 unsigned long csr, mc_seq;
814
815 INIT_LIST_HEAD(&req_list);
816 /* Set dma mode to fixed pattern */
817 csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
818 /* Enable once or continuous mode */
819 csr |= TEGRA_GPCDMA_CSR_ONCE;
820 /* Enable IRQ mask */
821 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
822 /* Enable the dma interrupt */
823 if (flags & DMA_PREP_INTERRUPT)
824 csr |= TEGRA_GPCDMA_CSR_IE_EOC;
825 /* Configure default priority weight for the channel */
826 csr |= (1 << TEGRA_GPCDMA_CSR_WEIGHT_SHIFT);
827
828 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
829 /* retain stream-id and clean rest */
830 mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID_MASK <<
831 TEGRA_GPCDMA_MCSEQ_STREAM_ID0_SHIFT);
832
833 /* Set the address wrapping */
834 mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
835 TEGRA_GPCDMA_MCSEQ_WRAP0_SHIFT;
836 mc_seq |= TEGRA_GPCDMA_MCSEQ_WRAP_NONE <<
837 TEGRA_GPCDMA_MCSEQ_WRAP1_SHIFT;
838
839 /* Program outstanding MC requests */
840 mc_seq |= (1 << TEGRA_GPCDMA_MCSEQ_REQ_COUNT_SHIFT);
841 /* Set burst size */
842 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
843
844 dma_desc = kzalloc(sizeof(struct tegra_dma_desc), GFP_NOWAIT);
845 if (!dma_desc) {
846 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
847 return NULL;
848 }
849 dma_desc->bytes_requested = 0;
850 dma_desc->bytes_transferred = 0;
851
852 if ((len & 3) || (dest & 3) ||
853 (len > tdc->tdma->chip_data->max_dma_count)) {
854 dev_err(tdc2dev(tdc),
855 "Dma length/memory address is not supported\n");
856 kfree(dma_desc);
857 return NULL;
858 }
859
860 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
861 if (!sg_req) {
862 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
863 kfree(dma_desc);
864 return NULL;
865 }
866
867 dma_desc->bytes_requested += len;
868 sg_req->ch_regs.src_ptr = 0;
869 sg_req->ch_regs.dst_ptr = dest;
> 870 sg_req->ch_regs.high_addr_ptr = ((dest >> 32) &
871 TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_MASK) <<
872 TEGRA_GPCDMA_HIGH_ADDR_DST_PTR_SHIFT;
873 sg_req->ch_regs.fixed_pattern = value;
874 /* Word count reg takes value as (N +1) words */
875 sg_req->ch_regs.wcount = ((len - 4) >> 2);
876 sg_req->ch_regs.csr = csr;
877 sg_req->ch_regs.mmio_seq = 0;
878 sg_req->ch_regs.mc_seq = mc_seq;
879 sg_req->configured = false;
880 sg_req->skipped = false;
881 sg_req->last_sg = false;
882 sg_req->dma_desc = dma_desc;
883 sg_req->req_len = len;
884 sg_req->last_sg = true;
885
886 list_add_tail(&sg_req->node, &tdc->pending_sg_req);
887
888 if (!tdc->isr_handler)
889 tdc->isr_handler = handle_once_dma_done;
890
891 tdc->pending_dma_desc = NULL;
892
893 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
894 }
895

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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