From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2152AC47277 for ; Thu, 6 Aug 2020 11:05:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12B1823123 for ; Thu, 6 Aug 2020 11:05:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="P7SeteD/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726204AbgHFHbc (ORCPT ); Thu, 6 Aug 2020 03:31:32 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19127 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727829AbgHFHah (ORCPT ); Thu, 6 Aug 2020 03:30:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 06 Aug 2020 00:28:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 06 Aug 2020 00:30:37 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Aug 2020 00:30:37 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 6 Aug 2020 07:30:35 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 6 Aug 2020 07:30:35 +0000 Received: from rgumasta-linux.nvidia.com (Not Verified[10.19.66.108]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 06 Aug 2020 00:30:34 -0700 From: Rajesh Gumasta To: , , , , , , , , CC: , Subject: [Patch v2 4/4] arm64: tegra: Add GPCDMA node in dt Date: Thu, 6 Aug 2020 13:00:06 +0530 Message-ID: <1596699006-9934-5-git-send-email-rgumasta@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596699006-9934-1-git-send-email-rgumasta@nvidia.com> References: <1596699006-9934-1-git-send-email-rgumasta@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596698937; bh=tc/XzjGQyzMqGlRhGZ2uP3xW0f0gkcCZd8iJhKBcbso=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=P7SeteD/QGAjy+rbn2b6p2uoyBqw5wmePGRGMbyMxhZ5ekn6hLdDX/LtLLxlQYEST kuf9ws+x6Om5IHJTfb3BMuOD/dvnHxVx9MLkoHK4KOUJKsxVbTIniWF01Nh9PNfkZc URIxXDD86tMaCDdmg9+hZClmFRe7FaZKwnvpXsiN7nzy+lC1zhyAQRqh/ESGqlgmlA KCRbkdNUmOjDQBbZw5l9/H1TsAv0RHrtibPj6XH8JQBPfgUvL58N7XqQpyKUQIli3k C9fwYTfJ1u8Dt9ZzoS+GgDcM7eaVCqv6SXVZJ73Xuga3CHn7lMqpLFL4z/kg81szVX 5pnB8XAS6+b1w== Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add device tree node for GPCDMA controller on Tegra186 target and Tegra194 target. Signed-off-by: Rajesh Gumasta --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 46 ++++++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++ 3 files changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 2fcaa2e..56ed8d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -54,6 +54,10 @@ }; }; + dma@2600000 { + status = "okay"; + }; + memory-controller@2c00000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 58100fb..91bb17e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -70,6 +70,52 @@ snps,rxpbl = <8>; }; + gpcdma: dma@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + nvidia,start-dma-channel-index = <1>; + dma-channels = <31>; + status = "disabled"; + }; + aconnect { compatible = "nvidia,tegra186-aconnect", "nvidia,tegra210-aconnect"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4bc187a..0bd67bd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -68,6 +68,50 @@ snps,rxpbl = <8>; }; + gpcdma: dma@2600000 { + compatible = "nvidia,tegra194-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA194_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + nvidia,start-dma-channel-index = <1>; + dma-channels = <31>; + status = "disabled"; + }; + aconnect@2900000 { compatible = "nvidia,tegra194-aconnect", "nvidia,tegra210-aconnect"; -- 2.7.4