From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: dmaengine: stm32-dma: fix residue calculation in stm32-dma From: Pierre Yves MORDRET Message-Id: <16d26967-a222-1dc5-58bd-b0c3fd60b767@st.com> Date: Wed, 24 Apr 2019 11:26:30 +0200 To: Arnaud Pouliquen , Vinod Koul Cc: Dan Williams , linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org List-ID: SGVsbG8KClJldmlld2VkLWJ5OiBQaWVycmUtWXZlcyBNT1JEUkVUIDxwaWVycmUteXZlcy5tb3Jk cmV0QHN0LmNvbT4KClRoYW5rcwoKT24gNC8yMy8xOSA1OjE4IFBNLCBBcm5hdWQgUG91bGlxdWVu IHdyb3RlOgo+IEhlbGxvIFZpbm9kLAo+IAo+IEp1c3QgYSBnZW50bGUgcmVtaW5kZXIsIGlmIHlv dSBjb3VsZCB0YWtlIGEgbW9tZW50IHRvIHJldmlldyB0aGlzIHBhdGNoLgo+IEZZSSwgdGhlIHBh dGNoIGhhcyBhbHJlYWR5IGJlZW4gaW50ZXJuYWxseSByZXZpZXdlZCBieSBQaWVycmUgWXZlcwo+ IG1vcmRyZXQuLi4KPiBIaXMgc2lnbi1vZmYgaXMgaW4gdGhlIGNvbW1pdCBtZXNzYWdlLgo+IAo+ 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[10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A064A156F; Wed, 24 Apr 2019 09:26:31 +0000 (GMT) Received: from [10.48.1.93] (10.75.127.45) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 24 Apr 2019 11:26:30 +0200 Subject: Re: [PATCH] dmaengine: stm32-dma: fix residue calculation in stm32-dma To: Arnaud Pouliquen , Vinod Koul CC: Dan Williams , , , References: <1553689316-6231-1-git-send-email-arnaud.pouliquen@st.com> <85a76ca4-6cad-e533-ff7b-64a660d1a2a0@st.com> From: Pierre Yves MORDRET Message-ID: <16d26967-a222-1dc5-58bd-b0c3fd60b767@st.com> Date: Wed, 24 Apr 2019 11:26:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <85a76ca4-6cad-e533-ff7b-64a660d1a2a0@st.com> Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-04-23_02:,, signatures=0 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Message-ID: <20190424092630.mGe9MOf59omRjQAdq7wi70r8q5_e_weINiFFpBXy11Q@z> Hello Reviewed-by: Pierre-Yves MORDRET Thanks On 4/23/19 5:18 PM, Arnaud Pouliquen wrote: > Hello Vinod, > > Just a gentle reminder, if you could take a moment to review this patch. > FYI, the patch has already been internally reviewed by Pierre Yves > mordret... > His sign-off is in the commit message. > > Thanks, > > Arnaud > > > On 3/27/19 1:21 PM, Arnaud Pouliquen wrote: >> During residue calculation. the DMA can switch to the next sg. When >> this race condition occurs, the residue returned value is not valid. >> Indeed the position in the sg returned by the hardware is the position >> of the next sg, not the current sg. >> Solution is to check the sg after the calculation to verify it. >> If a transition is detected we consider that the DMA has switched to >> the beginning of next sg. >> >> Signed-off-by: Arnaud Pouliquen >> Signed-off-by: Pierre-Yves MORDRET >> --- >> drivers/dma/stm32-dma.c | 70 ++++++++++++++++++++++++++++++++++++++++--------- >> 1 file changed, 57 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c >> index 4903a40..30309d2 100644 >> --- a/drivers/dma/stm32-dma.c >> +++ b/drivers/dma/stm32-dma.c >> @@ -1038,33 +1038,77 @@ static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) >> return ndtr << width; >> } >> >> +static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) >> +{ >> + struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); >> + struct stm32_dma_sg_req *sg_req; >> + u32 dma_scr, dma_smar, id; >> + >> + id = chan->id; >> + dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); >> + >> + if (!(dma_scr & STM32_DMA_SCR_DBM)) >> + return true; >> + >> + sg_req = &chan->desc->sg_req[chan->next_sg]; >> + >> + if (dma_scr & STM32_DMA_SCR_CT) { >> + dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); >> + return (dma_smar == sg_req->chan_reg.dma_sm0ar); >> + } >> + >> + dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); >> + >> + return (dma_smar == sg_req->chan_reg.dma_sm1ar); >> +} >> + >> static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, >> struct stm32_dma_desc *desc, >> u32 next_sg) >> { >> u32 modulo, burst_size; >> - u32 residue = 0; >> + u32 residue; >> + u32 n_sg = next_sg; >> + struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; >> int i; >> >> + residue = stm32_dma_get_remaining_bytes(chan); >> + >> /* >> - * In cyclic mode, for the last period, residue = remaining bytes from >> - * NDTR >> + * Calculate the residue means compute the descriptors >> + * information: >> + * - the sg currently transferred >> + * - the remaining position in this sg (NDTR). >> + * >> + * The issue is that a race condition can occur if DMA is >> + * running. DMA can have started to transfer the next sg before >> + * the position in sg is read. In this case the remaing position >> + * can correspond to the new sg position. >> + * The strategy implemented in the stm32 driver is to check the >> + * sg transition. If detected we can not trust the SxNDTR register >> + * value, this register can not be up to date during the transition. >> + * In this case we can assume that the dma is at the beginning of next >> + * sg so we calculate the residue in consequence. >> */ >> - if (chan->desc->cyclic && next_sg == 0) { >> - residue = stm32_dma_get_remaining_bytes(chan); >> - goto end; >> + >> + if (!stm32_dma_is_current_sg(chan)) { >> + n_sg++; >> + if (n_sg == chan->desc->num_sgs) >> + n_sg = 0; >> + residue = sg_req->len; >> } >> >> /* >> - * For all other periods in cyclic mode, and in sg mode, >> - * residue = remaining bytes from NDTR + remaining periods/sg to be >> - * transferred >> + * In cyclic mode, for the last period, residue = remaining bytes >> + * from NDTR, >> + * else for all other periods in cyclic mode, and in sg mode, >> + * residue = remaining bytes from NDTR + remaining >> + * periods/sg to be transferred >> */ >> - for (i = next_sg; i < desc->num_sgs; i++) >> - residue += desc->sg_req[i].len; >> - residue += stm32_dma_get_remaining_bytes(chan); >> + if (!chan->desc->cyclic || n_sg != 0) >> + for (i = n_sg; i < desc->num_sgs; i++) >> + residue += desc->sg_req[i].len; >> >> -end: >> if (!chan->mem_burst) >> return residue; >> >>