DMA Engine development
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From: Vinod Koul <vkoul@kernel.org>
To: Viresh Kumar <vireshk@kernel.org>,
	 Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	 Andy Shevchenko <andy@kernel.org>,
	Serge Semin <fancer.lancer@gmail.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jiri Slaby" <jirislaby@kernel.org>,
	dmaengine@vger.kernel.org, linux-serial@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND v4 0/6] dmaengine: dw: Fix src/dst addr width misconfig
Date: Thu, 29 Aug 2024 23:00:47 +0530	[thread overview]
Message-ID: <172495264758.385951.2350573756781126919.b4-ty@kernel.org> (raw)
In-Reply-To: <20240802075100.6475-1-fancer.lancer@gmail.com>


On Fri, 02 Aug 2024 10:50:45 +0300, Serge Semin wrote:
> The main goal of this series is to fix the data disappearance in case of
> the DW UART handled by the DW AHB DMA engine. The problem happens on a
> portion of the data received when the pre-initialized DEV_TO_MEM
> DMA-transfer is paused and then disabled. The data just hangs up in the
> DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel
> suspension (see the second commit log for details). On a way to find the
> denoted problem fix it was discovered that the driver doesn't verify the
> peripheral device address width specified by a client driver, which in its
> turn if unsupported or undefined value passed may cause DMA-transfer being
> misconfigured. It's fixed in the first patch of the series.
> 
> [...]

Applied, thanks!

[1/6] dmaengine: dw: Add peripheral bus width verification
      commit: e2c97d200ac3558e6c34258c96a01a0b9472292f
[2/6] dmaengine: dw: Add memory bus width verification
      commit: 5bb11aedb5309c232967ce490d7b826536f697c0
[3/6] dmaengine: dw: Simplify prepare CTL_LO methods
      commit: d34e8466c63389ef250c380cd615826afb2a049c
[4/6] dmaengine: dw: Define encode_maxburst() above prepare_ctllo() callbacks
      commit: 2f87a9671ed532fc088ef0b05e350637afdf001a
[5/6] dmaengine: dw: Simplify max-burst calculation procedure
      commit: 17d4353413a4d931e89b2c37106acae4a0972ad8
[6/6] dmaengine: dw: Unify ret-val local variables naming
      commit: 3f92ee7c4a4e2319d510eb2ddcfdd3105b235f0e

Best regards,
-- 
~Vinod



      parent reply	other threads:[~2024-08-29 17:30 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-02  7:50 [PATCH RESEND v4 0/6] dmaengine: dw: Fix src/dst addr width misconfig Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 1/6] dmaengine: dw: Add peripheral bus width verification Serge Semin
2024-09-14 19:12   ` Andy Shevchenko
2024-09-14 19:22     ` Serge Semin
2024-09-15 21:06       ` Ferry Toth
2024-09-16 11:43       ` Andy Shevchenko
2024-09-16 11:45         ` Andy Shevchenko
2024-09-16 11:57           ` Andy Shevchenko
2024-09-16 12:46             ` Andy Shevchenko
2024-09-19 14:04               ` Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 2/6] dmaengine: dw: Add memory " Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 3/6] dmaengine: dw: Simplify prepare CTL_LO methods Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 4/6] dmaengine: dw: Define encode_maxburst() above prepare_ctllo() callbacks Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 5/6] dmaengine: dw: Simplify max-burst calculation procedure Serge Semin
2024-08-02  7:50 ` [PATCH RESEND v4 6/6] dmaengine: dw: Unify ret-val local variables naming Serge Semin
2024-08-03 19:29 ` [PATCH RESEND v4 0/6] dmaengine: dw: Fix src/dst addr width misconfig Andy Shevchenko
2024-08-05 12:25   ` Serge Semin
2024-09-14 18:50     ` Andy Shevchenko
2024-09-14 19:06       ` Serge Semin
2024-09-14 19:08         ` Serge Semin
2024-09-15 11:43           ` Andy Shevchenko
2024-09-15 21:34             ` Serge Semin
2024-08-05 17:37 ` Vinod Koul
2024-08-29 17:30 ` Vinod Koul [this message]

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