[1/2] dt-bindings: dmaengine: Add Xilinx Video Framebuffer IP

[1/2] dt-bindings: dmaengine: Add Xilinx Video Framebuffer IP

[Vishal Sagar]

Add device tree binding documentation for the Xilinx Video Framebuffer IP.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: John Nichols <jnichol@xilinx.com>
Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
---
 .../bindings/dma/xilinx/xilinx_frmbuf.txt          | 76 ++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt

--
1.9.1

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diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt
new file mode 100644
index 0000000..a20fa6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt
@@ -0,0 +1,76 @@
+The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP
+block is used for reading video frame data from memory (FB Read) to the device
+and the other IP block is used for writing video frame data from the device
+to memory (FB Write).  Both the FB Read/Write IP blocks are aware of the
+format of the data being written to or read from memory including RGB and
+YUV in packed, planar, and semi-planar formats.  Because the FB Read/Write
+is format aware, only one buffer pointer is needed by the IP blocks even
+when planar or semi-planar format are used.
+
+FB Read Required propertie(s):
+- compatible		: Should be "xlnx,axi-frmbuf-rd-v2"
+
+Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it
+represented is no longer supported.
+
+FB Write Required propertie(s):
+- compatible		: Should be "xlnx,axi-frmbuf-wr-v2"
+
+Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it
+represented is no longer supported.
+
+Required Properties Common to both FB Read and FB Write:
+- #dma-cells		: should be 1
+- interrupt-parent	: Interrupt controller the interrupt is routed through
+- interrupts		: Should contain DMA channel interrupt
+- reset-gpios		: Should contain GPIO reset phandle
+- reg			: Memory map for module access
+- xlnx,dma-addr-width	: Size of dma address pointer in IP (either 32 or 64)
+- xlnx,vid-formats	: A list of strings indicating what video memory
+			  formats the IP has been configured to support.
+			  See VIDEO FORMATS table below and examples.
+
+VIDEO FORMATS
+The following table describes the legal string values to be used for
+the xlnx,vid-formats property.  To the left is the string value and the
+two columns to the right describe how this is mapped to an equivalent V4L2
+and DRM fourcc code---respectively---by the driver.
+
+IP FORMAT	DTS String	V4L2 Fourcc		DRM Fourcc
+-------------|----------------|----------------------|---------------------
+RGB8		bgr888		V4L2_PIX_FMT_RGB24	DRM_FORMAT_BGR888
+RGBX8		xbgr8888	<not supported>		DRM_FORMAT_XBGR8888
+YUYV8		yuyv		V4L2_PIX_FMT_YUYV	DRM_FORMAT_YUYV
+Y_UV8		nv16		V4L2_PIX_FMT_NV16	DRM_FORMAT_NV16
+Y_UV8_420	nv12		V4L2_PIX_FMT_NV12	DRM_FORMAT_NV12
+YUVX8		<none>		<not supported>		<not supported>
+YUV8		<none>		<not supported>		<not supported>
+Y8		y8		V4L2_PIX_FMT_GREY	<not supported>
+
+Examples
+
+FB Read Example:
+++++++++
+v_frmbuf_rd_0: v_frmbuf_rd@80000000 {
+	#dma-cells = <1>;
+	compatible = "xlnx,axi-frmbuf-rd-v2";
+	interrupt-parent = <&gic>;
+	interrupts = <0 92 4>;
+	reset-gpios = <&gpio 80 1>;
+	reg = <0x0 0x80000000 0x0 0x10000>;
+	xlnx,dma-addr-width = <32>;
+	xlnx,vid-formats = "bgr888","xbgr8888";
+};
+
+FB Write Example:
+++++++++
+v_frmbuf_wr_0: v_frmbuf_wr@80000000 {
+	#dma-cells = <1>;
+	compatible = "xlnx,axi-frmbuf-wr-v2";
+	interrupt-parent = <&gic>;
+	interrupts = <0 92 4>;
+	reset-gpios = <&gpio 80 1>;
+	reg = <0x0 0x80000000 0x0 0x10000>;
+	xlnx,dma-addr-width = <64>;
+	xlnx,vid-formats = "bgr888","yuyv","nv16","nv12";
+};

[1/2] dt-bindings: dmaengine: Add Xilinx Video Framebuffer IP

[Vinod Koul]

On Wed, Dec 20, 2017 at 02:00:17PM +0530, Vishal Sagar wrote:
> Add device tree binding documentation for the Xilinx Video Framebuffer IP.

pls send this or future versions to Rob and DT lists too..

> 
> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
> Signed-off-by: John Nichols <jnichol@xilinx.com>
> Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
> Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
> ---
>  .../bindings/dma/xilinx/xilinx_frmbuf.txt          | 76 ++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt
> new file mode 100644
> index 0000000..a20fa6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt
> @@ -0,0 +1,76 @@
> +The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP
> +block is used for reading video frame data from memory (FB Read) to the device
> +and the other IP block is used for writing video frame data from the device
> +to memory (FB Write).  Both the FB Read/Write IP blocks are aware of the
> +format of the data being written to or read from memory including RGB and
> +YUV in packed, planar, and semi-planar formats.  Because the FB Read/Write
> +is format aware, only one buffer pointer is needed by the IP blocks even
> +when planar or semi-planar format are used.
> +
> +FB Read Required propertie(s):
> +- compatible		: Should be "xlnx,axi-frmbuf-rd-v2"
> +
> +Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it
> +represented is no longer supported.
> +
> +FB Write Required propertie(s):
> +- compatible		: Should be "xlnx,axi-frmbuf-wr-v2"
> +
> +Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it
> +represented is no longer supported.
> +
> +Required Properties Common to both FB Read and FB Write:
> +- #dma-cells		: should be 1
> +- interrupt-parent	: Interrupt controller the interrupt is routed through
> +- interrupts		: Should contain DMA channel interrupt
> +- reset-gpios		: Should contain GPIO reset phandle
> +- reg			: Memory map for module access
> +- xlnx,dma-addr-width	: Size of dma address pointer in IP (either 32 or 64)
> +- xlnx,vid-formats	: A list of strings indicating what video memory
> +			  formats the IP has been configured to support.
> +			  See VIDEO FORMATS table below and examples.
> +
> +VIDEO FORMATS
> +The following table describes the legal string values to be used for
> +the xlnx,vid-formats property.  To the left is the string value and the
> +two columns to the right describe how this is mapped to an equivalent V4L2
> +and DRM fourcc code---respectively---by the driver.
> +
> +IP FORMAT	DTS String	V4L2 Fourcc		DRM Fourcc
> +-------------|----------------|----------------------|---------------------
> +RGB8		bgr888		V4L2_PIX_FMT_RGB24	DRM_FORMAT_BGR888
> +RGBX8		xbgr8888	<not supported>		DRM_FORMAT_XBGR8888
> +YUYV8		yuyv		V4L2_PIX_FMT_YUYV	DRM_FORMAT_YUYV
> +Y_UV8		nv16		V4L2_PIX_FMT_NV16	DRM_FORMAT_NV16
> +Y_UV8_420	nv12		V4L2_PIX_FMT_NV12	DRM_FORMAT_NV12
> +YUVX8		<none>		<not supported>		<not supported>
> +YUV8		<none>		<not supported>		<not supported>
> +Y8		y8		V4L2_PIX_FMT_GREY	<not supported>
> +
> +Examples
> +
> +FB Read Example:
> +++++++++
> +v_frmbuf_rd_0: v_frmbuf_rd@80000000 {
> +	#dma-cells = <1>;
> +	compatible = "xlnx,axi-frmbuf-rd-v2";
> +	interrupt-parent = <&gic>;
> +	interrupts = <0 92 4>;
> +	reset-gpios = <&gpio 80 1>;
> +	reg = <0x0 0x80000000 0x0 0x10000>;
> +	xlnx,dma-addr-width = <32>;
> +	xlnx,vid-formats = "bgr888","xbgr8888";
> +};
> +
> +FB Write Example:
> +++++++++
> +v_frmbuf_wr_0: v_frmbuf_wr@80000000 {
> +	#dma-cells = <1>;
> +	compatible = "xlnx,axi-frmbuf-wr-v2";
> +	interrupt-parent = <&gic>;
> +	interrupts = <0 92 4>;
> +	reset-gpios = <&gpio 80 1>;
> +	reg = <0x0 0x80000000 0x0 0x10000>;
> +	xlnx,dma-addr-width = <64>;
> +	xlnx,vid-formats = "bgr888","yuyv","nv16","nv12";
> +};
> --
> 1.9.1
> 
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