From: Vinod Koul <vinod.koul@intel.com>
To: Kedareswara rao Appana <appana.durga.rao@xilinx.com>
Cc: dan.j.williams@intel.com, michal.simek@xilinx.com,
appanad@xilinx.com, lars@metafoo.de, akinobu.mita@gmail.com,
joabreu@synopsys.com, mike.looijmans@topic.nl,
kedare06@gmail.com, dmaengine@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [v2,2/4] dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma
Date: Mon, 8 Jan 2018 16:25:15 +0530 [thread overview]
Message-ID: <20180108105515.GG18649@localhost> (raw)
On Wed, Jan 03, 2018 at 12:12:09PM +0530, Kedareswara rao Appana wrote:
> If the hardware is configured for Scatter Gather(SG) mode,
> and hardware is idle, in the control register SG mode bit
> must be set to a 0 then back to 1 by the software, to force
> the CDMA SG engine to use a new value written to the CURDESC_PNTR
> register, failure to do so could result errors from the dmaengine.
Applied 2-4, thanks
next reply other threads:[~2018-01-08 10:55 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-08 10:55 Vinod Koul [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-01-03 6:42 [v2,2/4] dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma Kedareswara rao Appana
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