From: Vinod Koul <vinod.koul@intel.com>
To: Radhey Shyam Pandey <radheys@xilinx.com>
Cc: "dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
Appana Durga Kedareswara Rao <appanad@xilinx.com>,
"lars@metafoo.de" <lars@metafoo.de>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"'RADHEYCS@GMAIL.COM'" <RADHEYCS@GMAIL.COM>
Subject: [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit
Date: Mon, 23 Apr 2018 10:53:17 +0530 [thread overview]
Message-ID: <20180423052317.GZ6014@localhost> (raw)
On Tue, Apr 17, 2018 at 12:28:52PM +0000, Radhey Shyam Pandey wrote:
> > > + if ((seg->hw.status & XILINX_DMA_COMP_MASK) ||
> > > + (!chan->xdev->has_axieth_connected)) {
> >
> > why the second case ? That is not expalined in log?
> In the current implementation, delay timeout is enabled only for
> has_axieth_connected usecase. For ethernet, we need real-time processing
> while still having benefit of interrupt coalescing. Example: In RX interrupt
> coalescing is set to 0x3. Without delay timeout, DMA engine will wait for
> all frames and then issue completion interrupt. In ethernet usecase, this
> can introduce huge latencies. Delay timeout interrupt will trigger if delay
> time period has expired and we can notify dma client with received frames.
>
> The second case is added to keep the previous implementation as is.(i.e when
> Delay timeout interrupt is not enabled - move all active desc to done list).
> Sure I will add a description for it in the commit log.
That should help, it didn't seem to have anything to do with log or other
changes, please keep in mind again that changelog should describe the change
and help ppl review...
next reply other threads:[~2018-04-23 5:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-23 5:23 Vinod Koul [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-04-17 12:28 [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2018-04-11 9:11 Vinod Koul
2018-04-02 10:39 Radhey Shyam Pandey
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