* [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
@ 2018-09-28 13:01 Pierre Yves MORDRET
0 siblings, 0 replies; 3+ messages in thread
From: Pierre Yves MORDRET @ 2018-09-28 13:01 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Mark Rutland, Alexandre Torgue,
Maxime Coquelin, Dan Williams, devicetree, dmaengine,
linux-arm-kernel, linux-kernel
Cc: Pierre-Yves MORDRET
From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
This patch adds the description of the 2 properties needed to support M2M
transfer triggered by STM32 DMA when his transfer is complete.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
---
Version history:
v3:
v2:
* rework content
v1:
* Initial
---
---
Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
index d18772d..27c2812 100644
--- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
+++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
@@ -10,7 +10,7 @@ Required properties:
- interrupts: Should contain the MDMA interrupt.
- clocks: Should contain the input clock of the DMA instance.
- resets: Reference to a reset controller asserting the DMA controller.
-- #dma-cells : Must be <5>. See DMA client paragraph for more details.
+- #dma-cells : Must be <6>. See DMA client paragraph for more details.
Optional properties:
- dma-channels: Number of DMA channels supported by the controller.
@@ -26,7 +26,7 @@ Example:
interrupts = <122>;
clocks = <&timer_clk>;
resets = <&rcc 992>;
- #dma-cells = <5>;
+ #dma-cells = <6>;
dma-channels = <16>;
dma-requests = <32>;
st,ahb-addr-masks = <0x20000000>, <0x00000000>;
@@ -35,8 +35,8 @@ Example:
* DMA client
DMA clients connected to the STM32 MDMA controller must use the format
-described in the dma.txt file, using a five-cell specifier for each channel:
-a phandle to the MDMA controller plus the following five integer cells:
+described in the dma.txt file, using a six-cell specifier for each channel:
+a phandle to the MDMA controller plus the following six integer cells:
1. The request line number
2. The priority level
@@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells:
if no HW ack signal is used by the MDMA client
5. A 32bit mask specifying the value to be written to acknowledge the request
if no HW ack signal is used by the MDMA client
+6. A bitfield value specifying if the MDMA client wants to generate M2M
+ transfer with HW trigger (1) or not (0). This bitfield should be only
+ enabled for M2M transfer triggered by STM32 DMA client. The memory devices
+ involved in this kind of transfer are SRAM and DDR.
Example:
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
@ 2018-10-07 14:59 Vinod Koul
0 siblings, 0 replies; 3+ messages in thread
From: Vinod Koul @ 2018-10-07 14:59 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>
> This patch adds the description of the 2 properties needed to support M2M
> transfer triggered by STM32 DMA when his transfer is complete.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v3:
> v2:
> * rework content
> v1:
> * Initial
> ---
> ---
> Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> index d18772d..27c2812 100644
> --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
> @@ -10,7 +10,7 @@ Required properties:
> - interrupts: Should contain the MDMA interrupt.
> - clocks: Should contain the input clock of the DMA instance.
> - resets: Reference to a reset controller asserting the DMA controller.
> -- #dma-cells : Must be <5>. See DMA client paragraph for more details.
> +- #dma-cells : Must be <6>. See DMA client paragraph for more details.
can you update the example for 6 cells?
Also what happens to dts using 5 cells..
>
> Optional properties:
> - dma-channels: Number of DMA channels supported by the controller.
> @@ -26,7 +26,7 @@ Example:
> interrupts = <122>;
> clocks = <&timer_clk>;
> resets = <&rcc 992>;
> - #dma-cells = <5>;
> + #dma-cells = <6>;
> dma-channels = <16>;
> dma-requests = <32>;
> st,ahb-addr-masks = <0x20000000>, <0x00000000>;
> @@ -35,8 +35,8 @@ Example:
> * DMA client
>
> DMA clients connected to the STM32 MDMA controller must use the format
> -described in the dma.txt file, using a five-cell specifier for each channel:
> -a phandle to the MDMA controller plus the following five integer cells:
> +described in the dma.txt file, using a six-cell specifier for each channel:
> +a phandle to the MDMA controller plus the following six integer cells:
>
> 1. The request line number
> 2. The priority level
> @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells:
> if no HW ack signal is used by the MDMA client
> 5. A 32bit mask specifying the value to be written to acknowledge the request
> if no HW ack signal is used by the MDMA client
> +6. A bitfield value specifying if the MDMA client wants to generate M2M
> + transfer with HW trigger (1) or not (0). This bitfield should be only
> + enabled for M2M transfer triggered by STM32 DMA client. The memory devices
> + involved in this kind of transfer are SRAM and DDR.
>
> Example:
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [v3,3/7] dt-bindings: stm32-mdma: Add DMA/MDMA chaining support bindings
@ 2018-10-09 8:17 Pierre Yves MORDRET
0 siblings, 0 replies; 3+ messages in thread
From: Pierre Yves MORDRET @ 2018-10-09 8:17 UTC (permalink / raw)
To: Vinod
Cc: Rob Herring, Mark Rutland, Alexandre Torgue, Maxime Coquelin,
Dan Williams, devicetree, dmaengine, linux-arm-kernel,
linux-kernel
On 10/07/2018 04:59 PM, Vinod wrote:
> On 28-09-18, 15:01, Pierre-Yves MORDRET wrote:
>> From: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>>
>> This patch adds the description of the 2 properties needed to support M2M
>> transfer triggered by STM32 DMA when his transfer is complete.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> Version history:
>> v3:
>> v2:
>> * rework content
>> v1:
>> * Initial
>> ---
>> ---
>> Documentation/devicetree/bindings/dma/stm32-mdma.txt | 12 ++++++++----
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-mdma.txt b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> index d18772d..27c2812 100644
>> --- a/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> +++ b/Documentation/devicetree/bindings/dma/stm32-mdma.txt
>> @@ -10,7 +10,7 @@ Required properties:
>> - interrupts: Should contain the MDMA interrupt.
>> - clocks: Should contain the input clock of the DMA instance.
>> - resets: Reference to a reset controller asserting the DMA controller.
>> -- #dma-cells : Must be <5>. See DMA client paragraph for more details.
>> +- #dma-cells : Must be <6>. See DMA client paragraph for more details.
>
> can you update the example for 6 cells?
of course.
>
> Also what happens to dts using 5 cells..
They are not managed, but it should. I will update this flaw. Thanks for
pointing this out.
>
>>
>> Optional properties:
>> - dma-channels: Number of DMA channels supported by the controller.
>> @@ -26,7 +26,7 @@ Example:
>> interrupts = <122>;
>> clocks = <&timer_clk>;
>> resets = <&rcc 992>;
>> - #dma-cells = <5>;
>> + #dma-cells = <6>;
>> dma-channels = <16>;
>> dma-requests = <32>;
>> st,ahb-addr-masks = <0x20000000>, <0x00000000>;
>> @@ -35,8 +35,8 @@ Example:
>> * DMA client
>>
>> DMA clients connected to the STM32 MDMA controller must use the format
>> -described in the dma.txt file, using a five-cell specifier for each channel:
>> -a phandle to the MDMA controller plus the following five integer cells:
>> +described in the dma.txt file, using a six-cell specifier for each channel:
>> +a phandle to the MDMA controller plus the following six integer cells:
>>
>> 1. The request line number
>> 2. The priority level
>> @@ -76,6 +76,10 @@ a phandle to the MDMA controller plus the following five integer cells:
>> if no HW ack signal is used by the MDMA client
>> 5. A 32bit mask specifying the value to be written to acknowledge the request
>> if no HW ack signal is used by the MDMA client
>> +6. A bitfield value specifying if the MDMA client wants to generate M2M
>> + transfer with HW trigger (1) or not (0). This bitfield should be only
>> + enabled for M2M transfer triggered by STM32 DMA client. The memory devices
>> + involved in this kind of transfer are SRAM and DDR.
>>
>> Example:
>>
>> --
>> 2.7.4
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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