From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [7/7] dmaengine: stm32-dma: properly mask irq bits From: Joel Fernandes Message-Id: <20181009054752.145978-8-joel@joelfernandes.org> Date: Mon, 8 Oct 2018 22:47:52 -0700 To: stable@vger.kernel.org Cc: Pierre Yves MORDRET , Antonio Borneo , Vinod Koul , gregkh@linuxfoundation.org, Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "Joel Fernandes (Google)" , "moderated list:ARM/STM32 ARCHITECTURE" , linux-kernel@vger.kernel.org, Maxime Coquelin List-ID: RnJvbTogUGllcnJlIFl2ZXMgTU9SRFJFVCA8cGllcnJlLXl2ZXMubW9yZHJldEBzdC5jb20+CgpB IHNpbmdsZSByZWdpc3RlciBvZiB0aGUgY29udHJvbGxlciBob2xkcyB0aGUgaW5mb3JtYXRpb24g Zm9yIGZvdXIgZG1hCmNoYW5uZWxzLgpUaGUgZnVuY3Rpb25zIHN0bTMyX2RtYV9pcnFfc3RhdHVz KCkgZG9uJ3QgbWFzayB0aGUgcmVsZXZhbnQgYml0cyBhZnRlcgp0aGUgc2hpZnQsIHRodXMgYWRq YWNlbnQgY2hhbm5lbCdzIHN0YXR1cyBpcyBhbHNvIHJlcG9ydGVkIGluIHRoZSByZXR1cm5lZAp2 YWx1ZS4KRml4ZWQgYnkgbWFza2luZyB0aGUgdmFsdWUgYmVmb3JlIHJldHVybmluZyBpdC4KClNp bWlsYXJseSwgdGhlIGZ1bmN0aW9uIHN0bTMyX2RtYV9pcnFfY2xlYXIoKSBkb24ndCBtYXNrIHRo ZSBpbnB1dCB2YWx1ZQpiZWZvcmUgc2hpZnRpbmcgaXQsIHRodXMgYW4gaW5jb3JyZWN0IGlucHV0 IHZhbHVlIGNvdWxkIGRpc2FibGUgdGhlCmludGVycnVwdHMgb2YgYWRqYWNlbnQgY2hhbm5lbHMu CkZpeGVkIGJ5IG1hc2tpbmcgdGhlIGlucHV0IHZhbHVlIGJlZm9yZSB1c2luZyBpdC4KClNpZ25l ZC1vZmYtYnk6IFBpZXJyZS1ZdmVzIE1PUkRSRVQgPHBpZXJyZS15dmVzLm1vcmRyZXRAc3QuY29t PgpTaWduZWQtb2ZmLWJ5OiBBbnRvbmlvIEJvcm5lbyA8Ym9ybmVvLmFudG9uaW9AZ21haWwuY29t PgpTaWduZWQtb2ZmLWJ5OiBWaW5vZCBLb3VsIDx2aW5vZC5rb3VsQGludGVsLmNvbT4KLS0tCiBk cml2ZXJzL2RtYS9zdG0zMi1kbWEuYyB8IDcgKysrKysrLQogMSBmaWxlIGNoYW5nZWQsIDYgaW5z ZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1hL3N0bTMy LWRtYS5jIGIvZHJpdmVycy9kbWEvc3RtMzItZG1hLmMKaW5kZXggMDVhMjk3NGNkMmMwLi44YzU4 MDczNjJhMjUgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZG1hL3N0bTMyLWRtYS5jCisrKyBiL2RyaXZl cnMvZG1hL3N0bTMyLWRtYS5jCkBAIC0zOCw2ICszOCwxMCBAQAogI2RlZmluZSBTVE0zMl9ETUFf VEVJCQkJQklUKDMpIC8qIFRyYW5zZmVyIEVycm9yIEludGVycnVwdCAqLwogI2RlZmluZSBTVE0z Ml9ETUFfRE1FSQkJCUJJVCgyKSAvKiBEaXJlY3QgTW9kZSBFcnJvciBJbnRlcnJ1cHQgKi8KICNk ZWZpbmUgU1RNMzJfRE1BX0ZFSQkJCUJJVCgwKSAvKiBGSUZPIEVycm9yIEludGVycnVwdCAqLwor I2RlZmluZSBTVE0zMl9ETUFfTUFTS0kJCQkoU1RNMzJfRE1BX1RDSSBcCisJCQkJCSB8IFNUTTMy X0RNQV9URUkgXAorCQkJCQkgfCBTVE0zMl9ETUFfRE1FSSBcCisJCQkJCSB8IFNUTTMyX0RNQV9G RUkpCiAKIC8qIERNQSBTdHJlYW0geCBDb25maWd1cmF0aW9uIFJlZ2lzdGVyICovCiAjZGVmaW5l IFNUTTMyX0RNQV9TQ1IoeCkJCSgweDAwMTAgKyAweDE4ICogKHgpKSAvKiB4ID0gMC4uNyAqLwpA QCAtNDA1LDcgKzQwOSw3IEBAIHN0YXRpYyB1MzIgc3RtMzJfZG1hX2lycV9zdGF0dXMoc3RydWN0 IHN0bTMyX2RtYV9jaGFuICpjaGFuKQogCiAJZmxhZ3MgPSBkbWFfaXNyID4+ICgoKGNoYW4tPmlk ICYgMikgPDwgMykgfCAoKGNoYW4tPmlkICYgMSkgKiA2KSk7CiAKLQlyZXR1cm4gZmxhZ3M7CisJ cmV0dXJuIGZsYWdzICYgU1RNMzJfRE1BX01BU0tJOwogfQogCiBzdGF0aWMgdm9pZCBzdG0zMl9k bWFfaXJxX2NsZWFyKHN0cnVjdCBzdG0zMl9kbWFfY2hhbiAqY2hhbiwgdTMyIGZsYWdzKQpAQCAt NDIwLDYgKzQyNCw3IEBAIHN0YXRpYyB2b2lkIHN0bTMyX2RtYV9pcnFfY2xlYXIoc3RydWN0IHN0 bTMyX2RtYV9jaGFuICpjaGFuLCB1MzIgZmxhZ3MpCiAJICogSWYgKGNoICUgNCkgaXMgMiBvciAz LCBsZWZ0IHNoaWZ0IHRoZSBtYXNrIGJ5IDE2IGJpdHMuCiAJICogSWYgKGNoICUgNCkgaXMgMSBv ciAzLCBhZGRpdGlvbmFsbHkgbGVmdCBzaGlmdCB0aGUgbWFzayBieSA2IGJpdHMuCiAJICovCisJ ZmxhZ3MgJj0gU1RNMzJfRE1BX01BU0tJOwogCWRtYV9pZmNyID0gZmxhZ3MgPDwgKCgoY2hhbi0+ aWQgJiAyKSA8PCAzKSB8ICgoY2hhbi0+aWQgJiAxKSAqIDYpKTsKIAogCWlmIChjaGFuLT5pZCAm IDQpCg==