DMA Engine development
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From: Viresh Kumar <viresh.kumar@linaro.org>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Viresh Kumar <vireshk@kernel.org>,
	dmaengine@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
	stable@vger.kernel.org
Subject: [v2] dmaengine: dw: Fix FIFO size for Intel Merrifield
Date: Thu, 6 Dec 2018 09:51:10 +0530	[thread overview]
Message-ID: <20181206042110.o5omse6qqopcjoru@vireshk-i7> (raw)

On 05-12-18, 18:33, Andy Shevchenko wrote:
> Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
> i.e. 512 bytes instead of 1024.
> 
> Fix this by partitioning it as 64 bytes per channel.
> 
> Note, in the future we might switch to 'fifo-size' property instead of
> hard coded value.
> 
> Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/dma/dw/core.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

             reply	other threads:[~2018-12-06  4:21 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-06  4:21 Viresh Kumar [this message]
  -- strict thread matches above, loose matches on Subject: below --
2018-12-06  5:24 [v2] dmaengine: dw: Fix FIFO size for Intel Merrifield Vinod Koul
2018-12-05 16:33 Andy Shevchenko

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