DMA Engine development
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From: Vinod Koul <vkoul@kernel.org>
To: Alexandru Ardelean <alexandru.ardelean@analog.com>
Cc: dmaengine@vger.kernel.org, Dragos Bogdan <dragos.bogdan@analog.com>
Subject: Re: [PATCH] dmaengine: axi-dmac: Add support for interleaved cyclic transfers
Date: Tue, 21 May 2019 10:36:18 +0530	[thread overview]
Message-ID: <20190521050618.GT15118@vkoul-mobl> (raw)
In-Reply-To: <20190516070443.16219-1-alexandru.ardelean@analog.com>

On 16-05-19, 10:04, Alexandru Ardelean wrote:
> From: Dragos Bogdan <dragos.bogdan@analog.com>
> 
> The DMAC HDL core supports interleaved & cyclic transfers.
> An example use-case for this mode is when the controller is used as a
> video DMA.
> 
> This change sets the `cyclic` field to true, so that when the IRQ comes and
> the `axi_dmac_transfer_done()` callback is called (from the interrupt
> handler) the proper `vchan_cyclic_callback()` is called. This way the
> DMAEngine framework will process data correctly for interleaved + cyclic
> transfers.
> 
> This doesn't fix anything. It's an enhancement to the driver.

Applied, thanks

-- 
~Vinod

      reply	other threads:[~2019-05-21  5:06 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-16  7:04 [PATCH] dmaengine: axi-dmac: Add support for interleaved cyclic transfers Alexandru Ardelean
2019-05-21  5:06 ` Vinod Koul [this message]

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