From: Vinod Koul <vkoul@kernel.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: dmaengine@vger.kernel.org, Michal Simek <michal.simek@xilinx.com>,
Hyun Kwon <hyun.kwon@xilinx.com>,
Tejas Upadhyay <tejasu@xilinx.com>,
Satish Kumar Nagireddy <SATISHNA@xilinx.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>
Subject: Re: [PATCH v5 4/6] dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver
Date: Fri, 3 Jul 2020 23:02:39 +0530 [thread overview]
Message-ID: <20200703173239.GP273932@vkoul-mobl> (raw)
In-Reply-To: <20200528025228.31638-5-laurent.pinchart@ideasonboard.com>
On 28-05-20, 05:52, Laurent Pinchart wrote:
> +++ b/drivers/dma/xilinx/xilinx_dpdma.c
> @@ -0,0 +1,1554 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx ZynqMP DPDMA Engine driver
> + *
> + * Copyright (C) 2015 - 2019 Xilinx, Inc.
2020 please
> +static struct xilinx_dpdma_tx_desc *
> +xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
> +{
> + struct xilinx_dpdma_tx_desc *tx_desc;
> +
> + tx_desc = kzalloc(sizeof(*tx_desc), GFP_KERNEL);
GFP_NOWAIT please, this is called from a prep call so needs to be atomic
context
> +static int xilinx_dpdma_config(struct dma_chan *dchan,
> + struct dma_slave_config *config)
> +{
> + struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
> + unsigned long flags;
> + int ret = 0;
> +
> + if (config->direction != DMA_MEM_TO_DEV)
> + return -EINVAL;
sorry but direction is deprecated and supposed to be remove, can you
please remove this
> +
> + /*
> + * The destination address doesn't need to be specified as the DPDMA is
> + * hardwired to the destination (the DP controller). The transfer
> + * width, burst size and port window size are thus meaningless, they're
> + * fixed both on the DPDMA side and on the DP controller side.
> + */
> +
> + spin_lock_irqsave(&chan->lock, flags);
> +
> + /* Can't reconfigure a running channel. */
> + if (chan->running) {
> + ret = -EBUSY;
> + goto unlock;
> + }
why does this part matter? The configuration is passed here and should
be applied to next descriptor submitted, channel can be busy.
> +
> + /*
> + * Abuse the slave_id to indicate that the channel is part of a video
> + * group.
> + */
Of course, what does video grp mean here?
> + if (chan->id >= ZYNQMP_DPDMA_VIDEO0 && chan->id <= ZYNQMP_DPDMA_VIDEO2)
> + chan->video_group = config->slave_id != 0;
so only thing we care here is slave_id? What about dma burst parameters?
--
~Vinod
next prev parent reply other threads:[~2020-07-03 17:32 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 2:52 [PATCH v5 0/6] dma: Add Xilinx ZynqMP DPDMA driver Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 1/6] dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 2/6] dmaengine: virt-dma: Use lockdep to check locking requirements Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 3/6] dmaengine: Add support for repeating transactions Laurent Pinchart
2020-07-03 17:10 ` Vinod Koul
2020-07-03 17:22 ` Laurent Pinchart
2020-07-03 17:37 ` Vinod Koul
2020-07-03 17:47 ` Laurent Pinchart
2020-07-03 17:54 ` Vinod Koul
2020-07-08 20:19 ` Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 4/6] dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver Laurent Pinchart
2020-07-03 17:32 ` Vinod Koul [this message]
2020-07-03 17:43 ` Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 5/6] dmaengine: xilinx: dpdma: Add debugfs support Laurent Pinchart
2020-05-28 2:52 ` [PATCH v5 6/6] arm64: dts: zynqmp: Add DPDMA node Laurent Pinchart
2020-06-29 9:30 ` [PATCH v5 0/6] dma: Add Xilinx ZynqMP DPDMA driver Laurent Pinchart
2020-06-29 9:56 ` Vinod Koul
2020-06-29 23:39 ` Laurent Pinchart
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