diff for duplicates of <20200916120955.7963-1-grygorii.strashko@ti.com> diff --git a/a/1.txt b/N1/1.txt index 8b13789..8e9f9c4 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1 +1,69 @@ +Now the K3 UDMA glue layer enable functions perform RMW operation on UDMA +RX/TX RT_CTL registers to set EN bit and enable channel, which is +incorrect, because only EN bit has to be set in those registers to enable +channel (all other bits should be cleared 0). +More over, this causes issues when bootloader leaves UDMA channel RX/TX +RT_CTL registers in incorrect state - TDOWN bit set, for example. As +result, UDMA channel will just perform teardown right after it's enabled. +Hence, fix it by writing correct values (EN=1) directly in UDMA channel +RX/TX RT_CTL registers in k3_udma_glue_enable_tx/rx_chn() functions. + +Fixes: d70241913413 ("dmaengine: ti: k3-udma: Add glue layer for non DMAengine users") +Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> +Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> +--- +Changes in v2: +- properly rebased on top of -master +- add ack from Peter Ujfalusi + + drivers/dma/ti/k3-udma-glue.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c +index 3a5d33ea5ebe..42c8ad10d75e 100644 +--- a/drivers/dma/ti/k3-udma-glue.c ++++ b/drivers/dma/ti/k3-udma-glue.c +@@ -378,17 +378,11 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn); + + int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) + { +- u32 txrt_ctl; +- +- txrt_ctl = UDMA_PEER_RT_EN_ENABLE; + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, +- txrt_ctl); ++ UDMA_PEER_RT_EN_ENABLE); + +- txrt_ctl = xudma_tchanrt_read(tx_chn->udma_tchanx, +- UDMA_CHAN_RT_CTL_REG); +- txrt_ctl |= UDMA_CHAN_RT_CTL_EN; + xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, +- txrt_ctl); ++ UDMA_CHAN_RT_CTL_EN); + + k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); + return 0; +@@ -1058,19 +1052,14 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_disable); + + int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) + { +- u32 rxrt_ctl; +- + if (rx_chn->remote) + return -EINVAL; + + if (rx_chn->flows_ready < rx_chn->flow_num) + return -EINVAL; + +- rxrt_ctl = xudma_rchanrt_read(rx_chn->udma_rchanx, +- UDMA_CHAN_RT_CTL_REG); +- rxrt_ctl |= UDMA_CHAN_RT_CTL_EN; + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, +- rxrt_ctl); ++ UDMA_CHAN_RT_CTL_EN); + + xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, + UDMA_PEER_RT_EN_ENABLE); +-- +2.17.1 diff --git a/a/content_digest b/N1/content_digest index 7401256..d640b56 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -10,5 +10,74 @@ " Grygorii Strashko <grygorii.strashko@ti.com>\0" "\00:1\0" "b\0" + "Now the K3 UDMA glue layer enable functions perform RMW operation on UDMA\n" + "RX/TX RT_CTL registers to set EN bit and enable channel, which is\n" + "incorrect, because only EN bit has to be set in those registers to enable\n" + "channel (all other bits should be cleared 0).\n" + "More over, this causes issues when bootloader leaves UDMA channel RX/TX\n" + "RT_CTL registers in incorrect state - TDOWN bit set, for example. As\n" + "result, UDMA channel will just perform teardown right after it's enabled.\n" + "\n" + "Hence, fix it by writing correct values (EN=1) directly in UDMA channel\n" + "RX/TX RT_CTL registers in k3_udma_glue_enable_tx/rx_chn() functions.\n" + "\n" + "Fixes: d70241913413 (\"dmaengine: ti: k3-udma: Add glue layer for non DMAengine users\")\n" + "Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\n" + "Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\n" + "---\n" + "Changes in v2:\n" + "- properly rebased on top of -master\n" + "- add ack from Peter Ujfalusi\n" + "\n" + " drivers/dma/ti/k3-udma-glue.c | 17 +++--------------\n" + " 1 file changed, 3 insertions(+), 14 deletions(-)\n" + "\n" + "diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c\n" + "index 3a5d33ea5ebe..42c8ad10d75e 100644\n" + "--- a/drivers/dma/ti/k3-udma-glue.c\n" + "+++ b/drivers/dma/ti/k3-udma-glue.c\n" + "@@ -378,17 +378,11 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn);\n" + " \n" + " int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)\n" + " {\n" + "-\tu32 txrt_ctl;\n" + "-\n" + "-\ttxrt_ctl = UDMA_PEER_RT_EN_ENABLE;\n" + " \txudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,\n" + "-\t\t\t txrt_ctl);\n" + "+\t\t\t UDMA_PEER_RT_EN_ENABLE);\n" + " \n" + "-\ttxrt_ctl = xudma_tchanrt_read(tx_chn->udma_tchanx,\n" + "-\t\t\t\t UDMA_CHAN_RT_CTL_REG);\n" + "-\ttxrt_ctl |= UDMA_CHAN_RT_CTL_EN;\n" + " \txudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,\n" + "-\t\t\t txrt_ctl);\n" + "+\t\t\t UDMA_CHAN_RT_CTL_EN);\n" + " \n" + " \tk3_udma_glue_dump_tx_rt_chn(tx_chn, \"txchn en\");\n" + " \treturn 0;\n" + "@@ -1058,19 +1052,14 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_disable);\n" + " \n" + " int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)\n" + " {\n" + "-\tu32 rxrt_ctl;\n" + "-\n" + " \tif (rx_chn->remote)\n" + " \t\treturn -EINVAL;\n" + " \n" + " \tif (rx_chn->flows_ready < rx_chn->flow_num)\n" + " \t\treturn -EINVAL;\n" + " \n" + "-\trxrt_ctl = xudma_rchanrt_read(rx_chn->udma_rchanx,\n" + "-\t\t\t\t UDMA_CHAN_RT_CTL_REG);\n" + "-\trxrt_ctl |= UDMA_CHAN_RT_CTL_EN;\n" + " \txudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,\n" + "-\t\t\t rxrt_ctl);\n" + "+\t\t\t UDMA_CHAN_RT_CTL_EN);\n" + " \n" + " \txudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,\n" + " \t\t\t UDMA_PEER_RT_EN_ENABLE);\n" + "-- \n" + 2.17.1 -964c60ba5aa3c6ddb0ae6c28816f6bdcb9ee9dbef6137685c13fea4d3027d94a +119b5850df4950d4400f8d3bf17d98b85fca0c0afe287b6a6de5e68169e6e18a
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